Patents by Inventor Steven C. Avanzino

Steven C. Avanzino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7776682
    Abstract: Disclosed are methods and systems for improving cell-to-cell repeatability of electrical performance in memory cells. The methods involve forming an electrically non-conducting material having ordered porosity over a passive layer. The ordered porosity can facilitate formation of conductive channels through which charge carriers can migrate across the otherwise non-conductive layer to facilitate changing a state of a memory cell. A barrier layer can optionally be formed over the non-conductive layer, and can have ordered porosity oriented in a manner substantially perpendicular to the conductive channels such that charge carries migrating across the non-conductive layer cannot permeate the barrier layer. The methods provide for the manufacture of microelectronic devices with cost-effective and electrically reliable memory cells.
    Type: Grant
    Filed: April 20, 2005
    Date of Patent: August 17, 2010
    Assignees: Spansion LLC, GlobalFoundries Inc.
    Inventors: Alexander Nickel, Suzette K. Pangrle, Steven C. Avanzino, Jeffrey Shields, Fei Wang, Minh Tran, Juri H. Krieger, Igor Sokolik
  • Patent number: 7465408
    Abstract: Disclosed are methods and systems of etching copper containing materials so that they have smooth and/or planar surface. In this connection, the systems and methods employ two different solutions to accomplish the etching. The first solution oxidizes the surface of the copper containing material and forms a passivating film. The second solution removes the passivating film in a controlable manner.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: December 16, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Steven C. Avanzino
  • Patent number: 7306988
    Abstract: Methods of making memory devices/cells are disclosed. A memory cell contains first and second electrode layers and a controllably conductive media therebetween. The controllably conductive media contains a copper sulfide-containing passive layer and active layer containing a Cu-doped tantalum oxide and/or titanium oxide layer. Methods of using the memory devices/cells, and devices such as computers containing the memory devices/cells are also disclosed.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: December 11, 2007
    Assignees: Advanced Micro Devices, Inc., Spansion LLC
    Inventors: Steven C. Avanzino, Wen Yu
  • Patent number: 7288782
    Abstract: Disclosed are methods for deposition of improved memory element films for semiconductor devices. The methods involve providing a hard mask over an upper surface of a metal line of a semiconductor substrate where vias are to be placed, recess etching the mask substantially in all upper surfaces except where vias are to be placed, depositing a Ta-containing capping layer over substantially all the metal line surfaces except the surface where vias are to be placed, polishing the Ta-containing capping layer to produce a damascened Ta-containing cap while exposing the metal line at the via forming surface, depositing a dielectric layer, patterning the dielectric layer to form a via, and depositing memory element films. The improved Ta—Cu interface of the subject invention mitigates and/or eliminates lateral growth of memory element films and copper voiding under the dielectric layer at the top surface of the metal line, and thereby enhances reliability and performance of semiconductor devices.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: October 30, 2007
    Assignees: Spansion LLC, Advanced Micro Devices, Inc.
    Inventors: Steven C. Avanzino, Amit P. Marathe
  • Patent number: 7235867
    Abstract: A die seal arrangement and method for making the same negatively biases the die edge seal of a die by connecting the die edge seal to a source of negative electrical potential, with respect to electrical ground. The die edge seal, made of copper, for example, has its oxidation reaction potential shifted to a region which is energetically unfavorable. This significantly retards or eliminates oxidation of the copper die edge seal at circuit operation temperature, thereby maintain the integrity and functionality of the die edge seal to protect active circuitry on the die, even when the die edge seal is exposed to moisture and air.
    Type: Grant
    Filed: November 1, 2004
    Date of Patent: June 26, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Roderick A. Augur, Steven C. Avanzino
  • Patent number: 7232765
    Abstract: Disclosed are methods for facilitating concurrent formation of copper vias and memory element structures. The methods involve forming vias over metal lines and forming copper plugs, wherein the copper plugs comprise memory element film forming copper plugs (memE copper plugs) and non-memory element forming copper plugs (non-memE copper plugs), forming a tantalum-containing cap over an upper surface of non-memE copper plugs, and depositing memory element films. The tantalum-containing cap prevents the formation of the memory element films in the non-memE copper plugs. The subject invention advantageously facilitates cost-effective manufacturing of semiconductor devices.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: June 19, 2007
    Assignees: Spansion LLC, Advanced Micro Devices, Inc.
    Inventors: Steven C. Avanzino, Nicholas H. Tripsas, Jeffrey A. Shields, Fei Wang, Richard P. Kingsborough, William Leonard, Suzette K. Pangrle
  • Patent number: 7157795
    Abstract: Electromigration and stress migration of Cu interconnects are significantly reduced by forming a composite capping layer comprising a layer of tantalum nitride on the upper surface of the inlaid Cu and a layer of ?-Ta on the titanium nitride layer. Embodiments include forming a recess in an upper surface of an upper surface of Cu inlaid in a dielectric layer, depositing a layer of titanium nitride of a thickness of 20 ? to 100 ? and then depositing a layer of ?-Ta at a thickness of 200 ? to 500 ?.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: January 2, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Darrell M. Erb, Steven C. Avanzino, Christy Mei-Chu Woo
  • Patent number: 7148144
    Abstract: Methods of forming copper sulfide regions or layers over a substrate are disclosed. The copper sulfide regions or layers are formed by contacting a sulfide compound with a substrate containing at least copper and contacting a copper vapor precursor with the substrate to form the copper sulfide layer. Methods of making a memory devices/cells containing a copper sulfide layer, methods of using the memory devices/cells, and devices such as computers containing the memory devices/cells are also disclosed.
    Type: Grant
    Filed: September 13, 2004
    Date of Patent: December 12, 2006
    Assignee: Spansion LLC
    Inventor: Steven C. Avanzino
  • Patent number: 7141482
    Abstract: Methods of making memory devices/cells are disclosed. First and second electrode layers and a controllably conductive media therebetween are formed over a dielectric layer that has a planar surface and at least one opening. The layers on the dielectric layer planar surface are removed so that the remaining second electrode surface in the opening is co-planar with the dielectric layer planar surface. Methods of using the memory devices/cells, and devices such as computers containing the memory devices/cells are also disclosed.
    Type: Grant
    Filed: November 2, 2004
    Date of Patent: November 28, 2006
    Assignee: Spansion LLC
    Inventor: Steven C. Avanzino
  • Patent number: 7129133
    Abstract: Disclosed are methods and structures for fabrication of reliable and efficient memory cells. The methods involve formation of a conformal diffusion barrier layer in a via, deposition of an electrode material in the via, removal of a certain portion of the electrode material from the via to expose a the portion of the diffusion barrier layer, converting the exposed portion of the diffusion barrier layer into an oxide, forming a memory element film, and forming and patterning a top electrode. Improved electrical conduction and data retention from the memory element of a memory cell by preventing short circuits and leakage of current through the conductive diffusion barrier layer, and thereby enhanced reliability and performance of a memory cell are obtained.
    Type: Grant
    Filed: September 13, 2004
    Date of Patent: October 31, 2006
    Assignee: Spansion LLC
    Inventors: Steven C. Avanzino, Minh Tran
  • Patent number: 7084062
    Abstract: Disclosed are methods for deposition of improved memory element films for semiconductor devices. The methods involve providing a hard mask over an upper surface of a metal line of a semiconductor substrate where vias are to be placed, recess etching the mask substantially in all upper surfaces except where vias are to be placed, depositing a Ta-containing capping layer over substantially all the metal line surfaces except the surface where vias are to be placed, polishing the Ta-containing capping layer to produce a damascened Ta-containing cap while exposing the metal line at the via forming surface, depositing a dielectric layer, patterning the dielectric layer to form a via to expose a portion of the metal line, and depositing memory element films.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: August 1, 2006
    Assignees: Advanced Micro Devices, Inc., Spansion LLC
    Inventors: Steven C. Avanzino, Amit P. Marathe
  • Patent number: 7011762
    Abstract: One aspect of the present invention relates to a wafer containing a semiconductor substrate, at least one metal layer formed over the semiconductor substrate, and at least one electrical sensor embedded at least one of on and in the wafer to facilitate real time monitoring of the metal layer as it progresses through a subtractive metallization process. Another aspect of the present relates to a system and method for monitoring a subtractive metallization process in real time in order to effectuate an immediate response in the on-going process. The system contains a wafer comprising at least one metal layer formed on a semiconductor substrate, at least one electrical sensor in contact with the wafer and operable to detect and transmit electrical activity associated with the wafer, and an electrical measurement station operable to process electrical activity detected and received from the electrical sensor for monitoring a subtractive metallization process in real-time.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: March 14, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christopher F. Lyons, Ramkumar Subramanian, Steven C. Avanzino
  • Patent number: 6989604
    Abstract: An integrated circuit having a substrate and a semiconductor device thereon. A stop layer over the substrate has a first dielectric layer formed thereon having an opening into which a first conformal barrier is formed. A first conformal barrier liner is formed in the opening, processed, and treated to improve adhesion. Portions of the first conformal barrier liner on the sidewalls act as a barrier to diffusion of conductor core material to the first dielectric layer. A conductor material is formed in the opening over the vertical portions of the first conformal barrier liner and the first stop layer.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: January 24, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christy Mei-Chu Woo, Minh Van Ngo, John E. Sanchez, Jr., Steven C. Avanzino
  • Patent number: 6979903
    Abstract: An integrated circuit is provided having a semiconductor substrate with a semiconductor device. A dielectric layer formed over the semiconductor substrate has an opening provided therein. The dielectric layer is of non-barrier dielectric material capable of being changed into a barrier dielectric material. The dielectric layer around the opening is changed into the barrier dielectric material and the conductor core material is deposited to fill the opening. The conductor core is processed to form a channel for the integrated circuit. This allows a selective conversion of dielectric materials with no diffusion barrier properties to be converted into good barrier materials which allows larger channels and shrinkage of the integrated circuit.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: December 27, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Steven C. Avanzino, Pin-Chin Connie Wang, Minh Van Ngo
  • Patent number: 6934032
    Abstract: A system and methodology for monitoring and/or controlling a semiconductor fabrication process is disclosed. Scatterometry and/or ellipsometry based techniques can be employed to facilitate providing measurement signals during a damascene phase of the fabrication process. The thickness of layers etched away during the process can be monitored and one or more fabrication components and/or operating parameters associated with the fabrication component(s) can be adjusted in response to the measurements to achieve desired results, such as to mitigate the formation of copper oxide during etching of a copper layer, for example.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: August 23, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ramkumar Subramanian, Steven C. Avanzino, Bharath Rangarajan, Bhanwar Singh
  • Patent number: 6841473
    Abstract: A manufacturing method for an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A cerium-conductor interconnect cap is disposed over the conductor core with a capping layer over the dielectric layer and the cerium-conductor interconnect cap.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: January 11, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Pin-Chin Connie Wang, Steven C. Avanzino
  • Patent number: 6836017
    Abstract: Low-k ILDs are protected from degradation during damascene processing by depositing a thin, conformal silicon carbide liner with a silicon-rich surface before barrier metal layer deposition. Embodiments include forming a dual damascene opening in porous low-k dielectric layers, depositing a thin silicon carbide liner with a silicon-rich surface lining the opening, depositing a barrier metal layer, such as a Ta/TaN composite, and filling the opening with Cu.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: December 28, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Minh Van Ngo, Christy Mei-Chu Woo, Steven C. Avanzino, John E. Sanchez, Jr., Suzette K. Pangrle
  • Patent number: 6808591
    Abstract: A systems and methodologies are provided for metal overetch control. Metal overetch processes are controlled by utilizing overetch device models to determine overetch times or overetch endpoints. The systems and methodologies reduce the need for manual testing and manual overetch characterization. An overetch system includes a metal etcher, a target device and an overetch controller. The target device is located in or on the metal etcher. The overetch controller is coupled to the metal etcher. The overetch controller controls overetching of the target device by the metal etcher. The overetch controller includes an overetch time controller, a set of etch control models and a control system.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: October 26, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi A. Phan, Bharath Rangarajan, Christopher F. Lyons, Steven C. Avanzino, Ramkumar Subramanian, Bhanwar Singh, Cyrus E. Tabery
  • Patent number: 6771356
    Abstract: A system for monitoring a fabrication process is provided. The system includes one or more light sources, each light source directing light to one or more gratings on a wafer. Light reflected from the gratings is collected by a measuring system that processes the collected light. The collected light is indicative of distortion due to stress at respective portions of the wafer. The measuring system provides distortion/stress related data to a processor that determines the acceptability of the distortion of the respective portions of the wafer. The collected light may be analyzed by scatterometry systems to produce scatterometry signatures associated with distortion and to produce feed-forward control information that can be employed to control semiconductor fabrication processes.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: August 3, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christopher F. Lyons, Bhanwar Singh, Steven C. Avanzino, Khoi A. Phan, Bharath Rangarajan, Ramkumar Subramanian, Cyrus E. Tabery
  • Publication number: 20040147117
    Abstract: Low-k ILDs are protected from degradation during damascene processing by depositing a thin, conformal silicon carbide liner with a silicon-rich surface before barrier metal layer deposition. Embodiments include forming a dual damascene opening in porous low-k dielectric layers, depositing a thin silicon carbide liner with a silicon-rich surface lining the opening, depositing a barrier metal layer, such as a Ta/TaN composite, and filling the opening with Cu.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 29, 2004
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Minh Van Ngo, Christy Mei-Chu Woo, Steven C. Avanzino, John E. Sanchez, Suzette K. Pangrle