Abstract: A system for characterizing a chemical mechanical polishing process is provided. The system includes a wafer that has a metal, polysilicon, and/or dielectric layer and/or substrate and a temperature sensor located in and/or on the metal, polysilicon and/or dielectric layer and/or substrate. The system also includes a temperature monitoring system that can read the wafer temperature from the temperature sensors and that can analyze the wafer temperature to characterize the chemical mechanical polishing process. Such characterization includes producing information concerning relationships between wafer temperature and polishing rate, polishing uniformity and introduction of defects during polishing. Such relationships are correlated with wafer temperature as related to parameters like polishing time, pressure, speed, slurry properties and wafer/metal layer properties.

Abstract: A method and article of manufacture of a semiconductor device having a cleaned source/drain surface and substantially uniform cobalt silicide deposited thereon. The method of the invention includes a precursor conventional step of an argon ion pre-sputter step which generally cleans the semiconductor device surfaces but ensures a resputtering of SiO2 to form SiOx species deposits on the source/drain surface of the device. An in situ treatment using silicon hydride species causes reduction of the SiOx species leaving a cleaned residual silicon which can accept a cobalt deposition to form a desired cobalt silicide layer on the source/drain surface.

Abstract: For fabricating an interconnect structure within an interconnect opening formed within a porous dielectric material, the interconnect opening is initially formed within a low-K precursor material that is not completely cured. The interconnect opening is then filled with a conductive fill material being contained within the interconnect opening and with a top surface of the conductive fill material within the interconnect opening being exposed. A capping material is formed on the top surface of the conductive fill material, and the capping material is an amorphous alloy or is a microcrystalline alloy having stuffed grain boundaries. A thermal curing process is then performed for curing the low-K precursor material to become a porous low-K dielectric material.

Abstract: Improved etch selectivity, barrier metal wetting and reduced interconnect capacitance are achieved by implementing damascene processing employing a graded middle etch stop layer comprising a first silicon carbide layer, a silicon-rich layer on the first silicon carbide, and a second silicon carbide layer on the silicon-rich layer. Embodiments include sequentially depositing a porous low-k dielectric layer over a lower capped Cu line, depositing the graded middle-etch stop layer, depositing a porous low-k dielectric layer on the graded middle-etch stop layer, forming a dual damascene opening exposing the silicon-rich surface at the bottom of the trench opening, depositing a seed layer, depositing a barrier middle layer, such as Ta or a Ta/TaN composite, and filling the opening with Cu.

Abstract: The electromigration resistance of capped Cu or Cu alloy interconnects is significantly improved by sequentially and contiguously treating the exposed planarized surface of in-laid Cu with a plasma containing NH3 and N2, ramping up the introduction of SiH4 and then initiating deposition of a silicon nitride capping layer. Embodiments include treating the exposed surface of in-laid Cu with a soft NH3 plasma diluted with N2, ramping up the introduction of SiH4 in two stages, and then initiating plasma enhanced chemical vapor deposition of a silicon nitride capping layer, while maintaining substantially the same pressure, N2 flow rate and NH3 flow rate during plasma treatment, SiH4 ramp up and silicon nitride deposition. Embodiments also include Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than about 3.9.

Abstract: A Ta barrier slurry for Chemical-Mechanical Polishing (CMP) during copper metallization contains an organic additive which suppresses formation of precipitates and copper staining.

Abstract: A method for manufacturing a field effect transistor (100) includes forming a gate structure (104) on a surface of a semiconductor substrate and forming first and second spacers (126, 126) on opposing sides of the gate structure. The method further includes etching a top portion of the gate structure and the first and second spacers to define a trench (1502). Subsequently, by a damascene process, at least a portion of the trench is filed with a barrier-high conductivity metal such as copper (1604) to form a T-gate.

Abstract: An integrated circuit and manufacturing method therefore is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate, and a channel dielectric layer formed on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening and a conductor core fills the opening over the barrier layer. Before planarization of the conductor core and the barrier layer, an anneal of the semiconductor substrate is performed at high temperatures of 400° C. and above to stimulate grain growth. After planarization, subsequent high temperature deposition of passivating or capping layers will not cause grain growth and hillocks will be suppressed.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. By using a polishing solution having a high selectivity from the conductor core to the barrier layer in conjunction with a fixed abrasive polish pad, a very thin barrier layer may be used without the conductor core and the dielectric layer being subject to erosion or dishing.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer formed over the semiconductor substrate has an opening provided therein. The dielectric layer is of non-barrier dielectric material capable of being changed into a barrier dielectric material. The dielectric layer around the opening is changed into the barrier dielectric material and the conductor core material is deposited to fill the opening. The conductor core is processed to form a channel for the integrated circuit.

Abstract: A deposition tool and a method for depositing a material within the recesses in a substrate of semiconductor wafer employs a rotatable diffuser that diffuses the plating material onto the top surface of a substrate. The diffuser is placed into contact with the semiconductor wafer and rotated while the plating material is applied through apertures in the diffuser. The plating material fills recesses patterned into the substrate of the semiconductor wafer but is prevented from forming to a significant degree on the top surface of the semiconductor wafer due to the contact and rotation of the diffuser. Since the plating material is not deposited on the top surface of the semiconductor wafer to any significant degree, chemical mechanical polishing (CMP) planarization is significantly reduced or completely eliminated.

Abstract: The electromigration resistance of capped Cu or Cu alloy interconnects is significantly improved by treating the exposed planarized surface of the Cu or Cu alloy with a plasma containing NH3 and N2 under mild steady state conditions, thereby avoiding sensitizing the Cu or Cu alloy surface before capping layer deposition with an attendant improvement in electromigration resistance and wafer-to-wafer uniformity. Embodiments include treating the Cu or Cu alloy surface with a plasma at a relatively high N2 flow rate of about 8,000 to about 9,200 sccm and a relatively low NH3 flow rate of about 210 to about 310 sccm.

Abstract: The present invention relates to a method for forming in-laid copper metallization capacitors in a trench serpentine form. In one aspect of the present invention, the method includes providing a semiconductor substrate having at least one trench formed therein. A first metal layer is deposited conformally onto a trench and substrate surface. The first metal layer is then anodized to form a conformal bilayer comprising an anodic (metal) oxide layer formed over the first metal layer. A copper-conductive metal layer is then deposited conformally over the metal oxide layer to facilitate electroplating of the trench and substrate surface. The trench and substrate surface is then electroplated with copper whereby the at least one trench is filled with copper.

Abstract: A method of manufacturing an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer with an opening provided therein is formed on the semiconductor substrate. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. The integrated circuit is annealed in an atmosphere containing ammonia. This results in reduced hydrogen accumulation, improved bonding, and reduced electro-migration.

Abstract: A method is provided for manufacturing an integrated circuit having a semiconductor substrate with a semiconductor device. A dielectric layer is formed on the semiconductor substrate and an opening is formed in the dielectric layer. A barrier layer is deposited to line the opening and conductor core is deposited to fill the channel opening over the barrier layer. By using a polishing solution having a dielectric protective characteristic, chemical-mechanical polishing of the conductor core and the barrier layer with the surface of the dielectric layer stops at the surface of the dielectric layer after planarization.

Abstract: The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of a dielectric layer over the surface of a substrate without scratching the dielectric layer and/or tungsten conductive contacts formed therein. In one embodiment, a chemical-mechanical polishing (CMP) process with non-oxidizer containing slurry is used to selectively remove the ARC layer at a rate which is significantly faster than the removal rates of the dielectric layer or the tungsten contacts. Further, an ARC CMP buffing process is used with a soft buffing pad in the CMP process to buff the dielectric layer and tungsten contacts during the ARC layer removal.

Abstract: A method is provided for manufacturing an integrated circuit on a semiconductor wafer having a semiconductor substrate with a semiconductor device thereon. A dielectric layer is formed on the semiconductor substrate and an opening is formed in the dielectric layer. A barrier layer is deposited to line the opening. A seed layer is deposited on the barrier layer and securely bonds to the barrier layer. A conductor layer is deposited to fill the channel opening over the barrier layer. A planarization technique is used to planarize the barrier, seed layer, and conductor layers to be coplanar with the dielectric layer to form a conductor channel. The semiconductor wafer is then subjected to a two step timed anneal.

Abstract: Embodiments of the invention comprise a new device and technique to realize an improved integrated circuit device that comprises an improved polysilicon upper surface. This improvement is achieved by approximately planarizing an upper surface of the polysilicon layer. First, the polysilicon layer is preferably formed as a relatively thicker layer as compared to the layer thickness in a conventional device. Then, a portion of the polysilicon layer is removed, preferably utilizing a chemical mechanical polish technique. Thus, this embodiment achieves a relatively planarized upper surface of the polysilicon layer. Then, for example, a conventional metal or silicide layer may be formed upon the relatively planarized polysilicon layer. This approximately planarized upper surface of the polysilicon layer allows for a silicide layer to be formed with a relative reduction in the amount and/or severity of the conventional word line voids and seams.

Abstract: A method is provided for manufacturing an integrated circuit on a semiconductor wafer having a semiconductor substrate with a semiconductor device thereon. A dielectric layer is formed on the semiconductor substrate and an opening is formed in the dielectric layer. A barrier layer is deposited to line the opening. A seed layer is deposited on the barrier layer and securely bonds to the barrier layer. A conductor layer is deposited to fill the channel opening over the barrier layer. A planarization technique is used to planarize the barrier, seed layer, and conductor layers to be coplanar with the dielectric layer to form a conductor channel. The semiconductor wafer is then subjected to a two step timed anneal.

Abstract: A selected passivating layer is purposely formed on an exposed surface of a Cu and/or Cu alloy interconnect member, thereby avoiding the adverse consequences stemming from formation of a thick copper oxide layer thereon. The passivating layer is formed by treating the exposed surface of the Cu or Cu alloy interconnect member: (a) with a copper corrosion-inhibiting chemical; or (b) by electroless plating a metal layer on the surface of the Cu or Cu alloy layer; or (c) depositing a metallic compound on the surface of the Cu or Cu alloy layer by CVD. The passivating layer can then be removed. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in an ILD, chemical mechanical polishing, then treating the exposed surface of the Cu/Cu alloy interconnect to form the passivating, layer thereon, and depositing a silicon nitride diffusion barrier layer thereon.