Abstract: The capacitance between a gate electrode of a transistor and local interconnect is reduced by employing SiC sidewall spacers on the side surfaces of the gate electrode when forming the source/drain regions with shallow extensions. Embodiments include forming SiC sidewall spacers at a width of about 500 .ANG. to about 800 .ANG. having a dielectric constant of less than about 3.2, depositing a silicon oxide inter-dielectric layer, and forming the local interconnect through the inter-dielectric layer. The resulting composite dielectric constant between the gate electrode and local interconnect is about 4.2 to about 4.7.

Abstract: The reliability of in-laid metallization patterns, e.g., of copper or a copper-based alloy is significantly enhanced by voidlessly filling recesses formed in the dielectric layer surface by an electroplating process. Embodiments of the present invention include preventing "pinching-off" of the recess opening due to formation of overhanging nucleation/seed layer deposits at the corners of the opening as a result of locally increased rates of deposition. Embodiments of the present invention also include providing a dual-layered dielectric layer comprising dielectric materials having different lateral etching rates when subjected to a preselected etching process, for selectively tapering the width of the recess mouth opening to provide a wider opening at the substrate surface, which tapered width profile effectively prevents formation of overhanging deposits, which overhanging deposits can result in occlusion and void formation during electroplating to fill the recesses.

Abstract: The dimensional precision and accuracy of sub-micron-sized, in-laid metallization patterns, e.g., of electroplated copper or copper alloy, formed in the surface of a dielectric layer are significantly improved by utilizing a layer of a sputter-resistant mask material formed of a high atomic mass metallic element or compound thereof during reactive ion etching of the dielectric layer by a fluorine-containing plasma for forming sub-micron-dimensioned recesses therein. After filling of the recesses, planarization, as by CMP, is conducted wherein excess thickness of the metal layer is removed, together with underlying portions of the sputter-resistant mask layer.

Abstract: The reliability of in-laid metallization patterns, e.g., of copper or copper alloy, is significantly enhanced by voidlessly filling recesses in a substrate by an electroplating process, wherein "pinching-off" of the recess opening due to earlier formation of overhanging nucleation/seed layer deposits at the corners of the opening as a result of increased rates of deposition thereat is prevented. Embodiments include selectively tapering the width of the recess mouth opening to provide a wider opening at the substrate surface by means of a directed beam etching or ablation process while rotating the substrate, which tapered width profile effectively prevents formation of overhanging deposits thereat which can result in occlusion and void formation during filling of the recesses by electroplating.

Abstract: In-laid metallization patterns, e.g., of copper or copper alloy, are formed in the surface of a dielectric layer with significantly improved reliability by voidlessly filling recesses formed in the dielectric layer surface by electroplating. Embodiments include preventing "pinching-off" of the recess opening due overhanging nucleation/seed layer deposits at the corners of the opening as a result of localized increased rates of deposition. Embodiments also include providing a dual-layered dielectric layer comprising different dielectric materials and performing a first, isotropic etching process of the upper (sacrificial) lamina of the dielectric layer for selectively tapering the width of the recess mouth opening to provide a wider opening at the substrate surface, followed by a second, anisotropic etching process for extending the recess at a substantially constant width for a predetermined depth into the lower lamina of the dielectric layer.

Abstract: The formation and/or growth of dendrites emanating from Cu or Cu alloy lines into a bordering open dielectric field are prevented or substantially reduced by chemically removing a portion of the surface from the dielectric field and from between the lines after CMP. Embodiments include removing up to 20 .ANG. of silicon oxide by buffing with a solution containing ammonium fluoride, diammonium hydrogen citrate, triammonium citrate, a surfactant and de-ionized water.

Abstract: An improved tungsten plug/Local Interconnect slurry for Chemical Mechanical Polishing which does not require inclusion of a chemical stabilizer. The slurry is made using a combination of two separate batch mixings of stable ingredients and Point-of Use mixing of portions of the two batches, whereby the oxidizers are combined with the coated abrasive mixture immediately prior to dispensing the slurry onto the polishing pad by combining selected flows from each of the two batches to form a total flow rate equal to the required rate of slurry flow onto the polishing pad.

Abstract: A polishing slurry composition and its method of making for planarization of silicon semiconductor wafers by chemical mechanical polishing of the wafer. A slurry formulation utilizing a ferric salt tungsten oxidizer, an ammonium persulfate titanium oxidizer, a fatty acid suspension agent, alumina particles with a small diameter and tight diameter range, coated with a solubility coating, and a chemical stabilizer, provides high tungsten and titanium polish rates with high selectivity to silicon dioxide, and good oxide defectivity for use in tungsten local interconnect applications. A method for making a tungsten slurry includes first thoroughly blending small diameter alumina particles with a tight diameter range in an aqueous concentrate with a suspension agent, then mixing with water and oxidizers. Ferric salt tungsten slurries made by this method provide excellent tungsten polish characteristics for via plug and local interconnect applications.

Abstract: A method for developing and characterizing a polish process for polishing an interlayer dielectric (ILD) layer for a specific product or a specific patterned metal layer is provided. A statistically-based model for ILD planarization by chemical mechanical polish (CMP) is used as a guide to determine, in an empirical manner, the proper amount of ILD polishing that will be required to planarize an ILD layer. The statistically-based model also shows the resulting ILD thicknesses to be expected. By relating the blank test wafer polished amount to the maximum amount of oxide removed from the field areas in the die and the total indicated range across the die, the ILD deposition thickness can be adjusted to attain the desired planarized ILD thickness. The attainment of local planarity, however, must be confirmed by an independent measurement technique. The polish process development methodology is extendible with respect to minimum interconnect feature size.

Abstract: A process and solution for cleaning Fe contaminants bound to a metallized semiconductor surface after CMP planarization. The solution comprises a PH buffered solution including hydrofluoric acid and a ligand selected from a group consisting of citrates and EDTA.

Abstract: An improved interconnect space filling process which provides voidless space filling for aspect ratio .ltoreq.1.88 by adding one step to the prior art process to change the aspect ratio of the space to be within specification aspect ratios for the older process. The added step is to apply a highly viscous single spin of SOG after applying a thin CVD PETEOS layer overtop the metallization.

Abstract: A process is provided for doping both sidewalls (26, 28) of isolation trenches (24, 26, 28) and connector regions (46, 48) between sources (58) and gate areas (62) and between drains (60) and gate areas in silicon CMOS devices. Appropriately doped glasses (16, 18, 30) formed on the silicon substrate (14) serve as the source of doping.

Abstract: A method is disclosed for making a highly planarized integrated circuit structure having deposited oxide portions planarized to the level of adjacent portions of the integrated circuit structure which comprises: deposition, over an integrated circuit structure having first portions at a height higher than the remainder of the integrated circuit structure, a conformal oxide layer; depositing a layer of a planarizing material such as polysilicon over the conformal oxide layer; polishing the structure a first time to expose the highest portions of the underlying conformal oxide layer; etching the structure a first time with an etchant system capable of removing the conformal oxide preferentially to the planarizing material; further polishing the structure a second time to remove planarizing material left from the first etching step; and then optionally etching the remainder of the structure to remove any remaining planarizing material and the remaining conformal oxide over the raised portions of the underlying i

Abstract: A method is disclosed for making a highly planarized integrated circuit structure having deposited oxide portions planarized to the level of adjacent portions of the integrated circuit structure which comprises: depositing, over an integrated circuit structure having first portions at a height higher than the remainder of the integrated circuit structure, a conformal oxide layer having a thickness which exceeds the height of said first portions above the remainder of the integrated circuit structure; forming a patterned mask layer over said deposited oxide layer with one or more openings therein in registry with the higher height first portions of the integrated circuit structure; etching exposed portions of said conformal oxide layer through the mask openings down to a level approximately equal to the level of the unexposed portion of the conformal oxide layer; removing the mask layer; and polishing the oxide layer to remove raised portions of the conformal oxide layer remaining after the etching step to for