Patents by Inventor Steven Howard Voldman

Steven Howard Voldman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7709924
    Abstract: A semiconductor structure and a method for operating the same. The method includes providing a semiconductor structure. The semiconductor structure includes first, second, third, and fourth doped semiconductor regions. The second doped semiconductor region is in direct physical contact with the first and third doped semiconductor regions. The fourth doped semiconductor region is in direct physical contact with the third doped semiconductor region. The first and second doped semiconductor regions are doped with a first doping polarity. The third and fourth doped semiconductor regions are doped with a second doping polarity. The method further includes (i) electrically coupling the first and fourth doped semiconductor regions to a first node and a second node of the semiconductor structure, respectively, and (ii) electrically charging the first and second nodes to first and second electric potentials, respectively. The first electric potential is different from the second electric potential.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: May 4, 2010
    Assignee: International Business Machines Corporation
    Inventor: Steven Howard Voldman
  • Publication number: 20100090277
    Abstract: A semiconductor structure and associated method of formation. The semiconductor structure includes a semiconductor substrate, a first doped transistor region of a first transistor and a first doped Source/Drain portion of a second transistor on the semiconductor substrate, a second gate dielectric layer and a second gate electrode region of the second transistor on the semiconductor substrate, a first gate dielectric layer and a first gate electrode region of the first transistor on the semiconductor substrate, and a second doped transistor region of the first transistor and a second doped Source/Drain portion of the second transistor on the semiconductor substrate. The first and second gate dielectric layers are sandwiched between and electrically insulate the semiconductor substrate from the first and second gate electrode regions, respectively. The first and second gate electrode regions are totally above and totally below, respectively, the top substrate surface.
    Type: Application
    Filed: December 17, 2009
    Publication date: April 15, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Steven Howard Voldman
  • Publication number: 20090236662
    Abstract: A semiconductor structure. The semiconductor structure includes a semiconductor substrate, a first transistor on the semiconductor substrate, and a guard ring on the semiconductor substrate. The semiconductor substrate includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface. The guard ring includes a semiconductor material doped with a doping polarity. A first doping profile of a first doped transistor region of the first transistor in the reference direction and a second doping profile of a first doped guard-ring region of the guard ring in the reference direction are essentially a same doping profile. The guard ring forms a closed loop around the first transistor.
    Type: Application
    Filed: June 1, 2009
    Publication date: September 24, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Steven Howard Voldman
  • Patent number: 7541247
    Abstract: A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure. The semiconductor structure includes a semiconductor substrate. The method further includes simultaneously forming a first doped transistor region of a first transistor and a first doped guard-ring region of a guard ring on the semiconductor substrate. The first doped transistor region and the first doped guard-ring region comprise dopants of a first doping polarity. The method further includes simultaneously forming a second doped transistor region of the first transistor and a second doped guard-ring region of the guard ring on the semiconductor substrate. The second doped transistor region and the second doped guard-ring region comprise dopants of the first doping polarity. The second doped guard-ring region is in direct physical contact with the first doped guard-ring region. The guard ring forms a closed loop around the first and second doped transistor regions.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: June 2, 2009
    Assignee: International Business Machines Corporation
    Inventor: Steven Howard Voldman
  • Publication number: 20090127619
    Abstract: An electrical structure and method of forming. The electrical structure includes a semiconductor substrate comprising a deep trench, an oxide liner layer is formed over an exterior surface of the deep trench, and a field effect transistor (FET) formed within the semiconductor substrate. The first FET includes a source structure, a drain structure, and a gate structure. The gate structure includes a gate contact connected to a polysilicon fill structure. The polysilicon fill structure is formed over the oxide liner layer and within the deep trench. The polysilicon fill structure is configured to flow current laterally across the polysilicon fill structure such that the current will flow parallel to a top surface of the semiconductor substrate.
    Type: Application
    Filed: November 20, 2007
    Publication date: May 21, 2009
    Inventors: Jeffrey Peter Gambino, Benjamin Thomas Voegeli, Steven Howard Voldman, Michael Joseph Zierak
  • Publication number: 20090020813
    Abstract: A semiconductor structure and a method forming the same. The method includes providing a semiconductor structure which includes a semiconductor substrate. The semiconductor substrate includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface. The method further includes simultaneously forming a first doped transistor region of a first transistor and a first doped Source/Drain portion of a second transistor on the semiconductor substrate. The first doped transistor region is not a portion of a Source/Drain region of the first transistor. The first doped transistor region and the first doped Source/Drain portion comprise dopants of a first doping polarity. The method further includes forming a second gate dielectric layer and a second gate electrode region of the second transistor on the semiconductor substrate. The second gate dielectric layer is sandwiched between and electrically insulates the second gate electrode region and the semiconductor substrate.
    Type: Application
    Filed: July 16, 2007
    Publication date: January 22, 2009
    Inventor: Steven Howard Voldman
  • Publication number: 20090020811
    Abstract: A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure. The semiconductor structure includes a semiconductor substrate. The method further includes simultaneously forming a first doped transistor region of a first transistor and a first doped guard-ring region of a guard ring on the semiconductor substrate. The first doped transistor region and the first doped guard-ring region comprise dopants of a first doping polarity. The method further includes simultaneously forming a second doped transistor region of the first transistor and a second doped guard-ring region of the guard ring on the semiconductor substrate. The second doped transistor region and the second doped guard-ring region comprise dopants of the first doping polarity. The second doped guard-ring region is in direct physical contact with the first doped guard-ring region. The guard ring forms a closed loop around the first and second doped transistor regions.
    Type: Application
    Filed: July 16, 2007
    Publication date: January 22, 2009
    Inventor: Steven Howard Voldman
  • Publication number: 20090020818
    Abstract: A semiconductor structure and a method for operating the same. The method includes providing a semiconductor structure. The semiconductor structure includes first, second, third, and fourth doped semiconductor regions. The second doped semiconductor region is in direct physical contact with the first and third doped semiconductor regions. The fourth doped semiconductor region is in direct physical contact with the third doped semiconductor region. The first and second doped semiconductor regions are doped with a first doping polarity. The third and fourth doped semiconductor regions are doped with a second doping polarity. The method further includes (i) electrically coupling the first and fourth doped semiconductor regions to a first node and a second node of the semiconductor structure, respectively, and (ii) electrically charging the first and second nodes to first and second electric potentials, respectively. The first electric potential is different from the second electric potential.
    Type: Application
    Filed: July 16, 2007
    Publication date: January 22, 2009
    Inventor: Steven Howard Voldman
  • Publication number: 20080273280
    Abstract: Diodes and method of fabricating diodes. A diode includes: an p-type single wall carbon nanotube; an n-type single wall carbon nanotube, the p-type single wall carbon nanotube in physical and electrical contact with the n-type single wall carbon nanotube; and a first metal pad in physical and electrical contact with the p-type single wall carbon nanotube and a second metal pad in physical and electrical contact with the n-type single wall carbon nanotube.
    Type: Application
    Filed: May 4, 2007
    Publication date: November 6, 2008
    Inventors: Jia Chen, Steven Howard Voldman
  • Publication number: 20080265363
    Abstract: A structure and method of fabricating the structure. The structure including: a dielectric isolation in a semiconductor substrate, the dielectric isolation extending in a direction perpendicular to a top surface of the substrate into the substrate a first distance, the dielectric isolation surrounding a first region and a second region of the substrate, a top surface of the dielectric isolation coplanar with the top surface of the substrate; a dielectric region in the second region of the substrate; the dielectric region extending in the perpendicular direction into the substrate a second distance, the first distance greater than the second distance; and a first device in the first region and a second device in the second region, the first device different from the second device, the dielectric region isolating a first element of the second device from a second element of the second device.
    Type: Application
    Filed: April 30, 2007
    Publication date: October 30, 2008
    Inventors: Jeffrey Peter Gambino, Steven Howard Voldman, Michael Joseph Zierak
  • Publication number: 20080265422
    Abstract: A structure for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a semiconductor substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures.
    Type: Application
    Filed: July 2, 2008
    Publication date: October 30, 2008
    Inventors: John Joseph Ellis-Monaghan, Jeffrey Peter Gambino, Timothy Dooling Sullivan, Steven Howard Voldman
  • Patent number: 7309898
    Abstract: A method and apparatus for improving the latchup tolerance of circuits embedded in an integrated circuit while avoiding the introduction of noise from such tolerance into the power rails.
    Type: Grant
    Filed: May 20, 2002
    Date of Patent: December 18, 2007
    Assignee: International Business Machines Corporation
    Inventors: Raminderpal Singh, Steven Howard Voldman
  • Patent number: 7020857
    Abstract: A method and apparatus for analyzing an integrated circuit design for pnpn structures which are likely to latchup or cause injection of noise into the substrate. Once qualifying pnpn structures are identified, the method and apparatus automatically inserts a noise and latchup suppression circuit of the designers' choice into the pnpn structure to eliminate the latchup and/or noise concerns.
    Type: Grant
    Filed: May 20, 2002
    Date of Patent: March 28, 2006
    Assignee: International Business Machines Corporation
    Inventors: Raminderpal Singh, Steven Howard Voldman
  • Patent number: 6826025
    Abstract: An integrated circuit having either or both ESD and noise suppression devices that use the inherent resistance in the substrate as an ESD trigger and/or part of the noise suppression.
    Type: Grant
    Filed: May 20, 2002
    Date of Patent: November 30, 2004
    Assignee: International Business Machines Corporation
    Inventors: Raminderpal Singh, Steven Howard Voldman
  • Patent number: 6774017
    Abstract: A semiconductor structure, and associated method of fabrication, comprising a substrate having a continuous buried oxide layer and having a plurality of trench isolation structures. The buried oxide layer may be located at more than one depth within the substrate. The geometry of the trench isolation structure may vary with depth. The trench isolation structure may touch or not touch the buried oxide layer. Two trench isolation structures may penetrate the substrate to the same depth or to different depths. The trench isolation structures provide insulative separation between regions within the substrate and the separated regions may contain semiconductor devices. The semiconductor structure facilitates the providing of digital and analog devices on a common wafer. A dual-depth buried oxide layer facilitates an asymmetric semiconductor structure.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: August 10, 2004
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey Scott Brown, Andres Bryant, Robert J. Gauthier, Jr., Randy William Mann, Steven Howard Voldman
  • Patent number: 6762918
    Abstract: A fuse state circuit for reading the state of a fuse that is enhanced to reduce the circuits susceptibility to ESD, EOS or CDM events.
    Type: Grant
    Filed: May 20, 2002
    Date of Patent: July 13, 2004
    Assignee: International Business Machines Corporation
    Inventor: Steven Howard Voldman
  • Patent number: 6720637
    Abstract: An SiGe device configured to exhibit high velocity saturation resistance characteristic for buffering large voltages at low currents, wherein for circuit applications, the SiGe device is connected in series with a circuit element for protection of the circuit element. Advantageously, the device may be exploited as a buffer element providing ESD circuit protection for receiver devices, power supply clamp circuits and I/O driver circuits.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: April 13, 2004
    Assignee: International Business Machines Corporation
    Inventor: Steven Howard Voldman
  • Patent number: 6710983
    Abstract: A magnetic head includes a GMR read head that is protected from electrostatic discharge (ESD) on a slider by a silicon germanium (SiGe) integrated circuit device. In a preferred embodiment the SiGe circuit device includes one or more silicon germanium heterojunction bipolar transistors (SiGe HBT) or silicon germanium carbon heterojunction bipolar transistors (SiGeC HBT) that is electrically connected across the electrical leads of the GMR read head. Particular electrical connection configurations with the SiGe circuit devices include diodic modes, npn modes, series cascade modes and two stage ESD network configurations. The silicon chip may be sandwiched between the slider body and the read/write head or the read/write head may be sandwiched between the slider body and the silicon chip.
    Type: Grant
    Filed: May 10, 2002
    Date of Patent: March 23, 2004
    Assignee: International Business Machines Corporation
    Inventor: Steven Howard Voldman
  • Publication number: 20040017640
    Abstract: A magneto-resistive read head having a “parasitic shield” provides an alternative path for currents associated with sparkovers, thus preventing such currents from damaging the read head. The parasitic shield is provided in close proximity to a conventional magnetic shield. The electrical potential of parasitic shield is held essentially equal to the electrical potential of the sensor element. If charges accumulate on the conventional shield, current will flow to the parasitic shield at a lower potential than would be required for current to flow between the conventional shield and the sensor element. Alternatively, conductive spark gap devices are electrically coupled to sensor element leads and to each magnetic shield. Each spark gap device is brought within very close proximity of the substrate to provide an alternative path for charge that builds up between the sensor element and the substrate to be discharged.
    Type: Application
    Filed: February 2, 2001
    Publication date: January 29, 2004
    Inventors: Timothy Scott Hughbanks, Neil Leslie Robertson, Steven Howard Voldman, Albert John Wallash
  • Publication number: 20030213978
    Abstract: A fuse state circuit for reading the state of a fuse that is enhanced to reduce the circuits susceptibility to ESD, EOS or CDM events.
    Type: Application
    Filed: May 20, 2002
    Publication date: November 20, 2003
    Applicant: International Business Machines Corporation
    Inventor: Steven Howard Voldman