Abstract: A method and apparatus for identifying parasitic pnpn structures in an integrated circuit, and automatically inserting a noise latchup suppression circuit in such identified pnpn structure.

Abstract: A fuse state circuit for reading the state of a fuse that is enhanced to reduce the circuits susceptibility to ESD, EOS or CDM events.

Abstract: A magnetic head includes a GMR read head that is protected from electrostatic discharge (ESD) on a slider by a silicon germanium (SiGe) integrated circuit device. In a preferred embodiment the SiGe circuit device includes one or more silicon germanium heterojunction bipolar transistors (SiGe HBT) or silicon germanium carbon heterojunction bipolar transistors (SiGeC HBT) that is electrically connected across the electrical leads of the GMR read head. Particular electrical connection configurations with the SiGe circuit devices include diodic modes, npn modes, series cascade modes and two stage ESD network configurations. The silicon chip may be sandwiched between the slider body and the read/write head or the read/write head may be sandwiched between the slider body and the silicon chip.

Abstract: A method of forming an integrated circuit interconnect level capacitor is disclosed. In an exemplary embodiment, the method includes depositing a first insulator layer over an interconnect level surface of a semiconductor substrate having active devices. First and second conductive lines are formed in the first insulator layer, and the first insulator layer is etched to form a trench therein between the first and second conductive lines. A first conductive layer is deposited over the first and second conductive lines the said trench. A second insulator layer is deposited over the first conductive layer, and a second conductive layer is deposited over the second insulator layer. Then, a third conductive line is formed and disposed in the trench, the third conductive line overlying the second conductive barrier layer.

Abstract: An SiGe device configured to exhibit high velocity saturation resistance characteristic for buffering large voltages at low currents, wherein for circuit applications, the SiGe device is connected in series with a circuit element for protection of the circuit element. Advantageously, the device may be exploited as a buffer element providing ESD circuit protection for receiver devices, power supply clamp circuits and I/O driver circuits.

Abstract: An SiGe device configured to exhibit high velocity saturation resistance characteristic for buffering large voltages at low currents, wherein for circuit applications, the SiGe device is connected in series with a circuit element for protection of the circuit element. Advantageously, the device may be exploited as a buffer element providing ESD circuit protection for receiver devices, power supply clamp circuits and I/O driver circuits.

Abstract: An ESD protective circuit is described which has a very low, variable turn-on threshold by using a shunting MOSFET which has an isolated substrate/body which is connected to an electrode that is provided in addition to the gate, source and drain electrodes. A variable gate voltage which is preferably a function of an ESD voltage is used to trigger the MOSFET into conduction. A voltage is applied to the substrate/body of the MOSFET to lower the turn-on voltage. The voltage on the substrate allows the turn-on voltage to be adjusted for different applications and/or to be adjusted dynamically to respond to events. The substrate voltage is also preferably derived from the ESD voltage. Preferably the MOSFET has an epitaxial region with an electrode and a subcollector with an electrode. The epitaxial region electrode can be connected to the gate to improve the turn-on performance. The subcollector electrode can be connected to the substrate/body electrode to contribute to lowering the turn-on voltage.

Abstract: An ESD clamping circuit arranged in a darlington configuration and constructed from SiGe or similar type material. The ESD clamping circuit includes additional level shifting circuitry in series with either the trigger or clamping device or both, thus allowing non-native voltages that exceed the BVCEO of the trigger and/or clamp devices.

Abstract: An ESD clamping circuit arranged in a darlington configuration and constructed from SiGe or similar type material. The ESD clamping circuit includes additional level shifting circuitry in series with either the trigger or clamping device or both, thus allowing non-native voltages that exceed the BVCEO of the trigger and/or clamp devices.

Abstract: A semiconductor structure, and associated method of fabrication, comprising a substrate having a continuous buried oxide layer and having a plurality of trench isolation structures. The buried oxide layer may be located at more than one depth within the substrate. The geometry of the trench isolation structure may vary with depth. The trench isolation structure may touch or not touch the buried oxide layer. Two trench isolation structures may penetrate the substrate to the same depth or to different depths. The trench isolation structures provide insulative separation between regions within the substrate and the separated regions may contain semiconductor devices. The semiconductor structure facilitates the providing of digital and analog devices on a common wafer. A dual-depth buried oxide layer facilitates an asymmetric semiconductor structure.

Abstract: A semiconductor structure, and associated method of fabrication, comprising a substrate having a continuous buried oxide layer and having a plurality of trench isolation structures. The buried oxide layer may be located at more than one depth within the substrate. The geometry of the trench isolation structure may vary with depth. The trench isolation structure may touch or not touch the buried oxide layer. Two trench isolation structures may penetrate the substrate to the same depth or to different depths. The trench isolation structures provide insulative separation between regions within the substrate and the separated regions may contain semiconductor devices. The semiconductor structure facilitates the providing of digital and analog devices on a common wafer. A dual-depth buried oxide layer facilitates an asymmetric semiconductor structure.

Abstract: A method of forming an integrated circuit interconnect level capacitor is disclosed. In an exemplary embodiment, the method includes depositing a first insulator layer over an interconnect level surface of a semiconductor substrate having active devices. First and second conductive lines are formed in the first insulator layer, and the first insulator layer is etched to form a trench therein between the first and second conductive lines. A first conductive layer is deposited over the first and second conductive lines the said trench. A second insulator layer is deposited over the first conductive layer, and a second conductive layer is deposited over the second insulator layer. Then, a third conductive line is formed and disposed in the trench, the third conductive line overlying the second conductive barrier layer.

Abstract: A ESD (electrostatic discharge) robust SiGe bipolar transistor is provided which comprises a substrate of a first conductivity type; a doped subcollector region of a second conductivity type formed on the substrate, the doped subcollector region including an epitaxial collector region which is defined between isolation trench regions; a first film comprising silicon and germanium formed on the doped subcollector region, the first film including a single crystal SiGe intrinsic base region and an extrinsic SiGe polysilicon base regions of the first conductivity type abutting the intrinsic base region; a second film comprising an emitter of the second conductivity type contained over the intrinsic base region formed by an emitter window mask and a second region formed outside of the emitter; a first doped region of the first conductivity type formed at a facet point between the intrinsic base region and one of the extrinsic base regions; a second doped region of said first conductivity type contained at the oute

Abstract: A SiGe ESD power clamp in a Darlington type configuration where the trigger device has a collector-to-emitter breakdown voltage (BVCEO) that is lower than that of the clamping device, and a frequency cutoff that is higher than that of the clamping device.

Abstract: An ESD protective circuit is described which has a very low, variable turn-on threshold by using a shunting MOSFET which has an isolated substrate/body which is connected to an electrode that is provided in addition to the gate, source and drain electrodes. A variable gate voltage which is preferably a function of an ESD voltage is used to trigger the MOSFET into conduction. A voltage is applied to the substrate/body of the MOSFET to lower the turn-on voltage. The voltage on the substrate allows the turn-on voltage to be adjusted for different applications and/or to be adjusted dynamically to respond to events. The substrate voltage is also preferably derived from the ESD voltage. Preferably the MOSFET has an epitaxial region with an electrode and a subcollector with an electrode. The epitaxial region electrode can be connected to the gate to improve the turn-on performance. The subcollector electrode can be connected to the substrate/body electrode to contribute to lowering the turn-on voltage.

Abstract: A ESD (electrostatic discharge) robust SiGe bipolar transistor is provided which comprises a substrate of a first conductivity type; a doped subcollector region of a second conductivity type formed on the substrate, the doped subcollector region including an epitaxial collector region which is defined between isolation trench regions; a first film comprising silicon and germanium formed on the doped subcollector region, the first film including a single crystal SiGe intrinsic base region and an extrinsic SiGe polysilicon base regions of the first conductivity type abutting the intrinsic base region; a second film comprising an emitter of the second conductivity type contained over the intrinsic base region formed by an emitter window mask and a second region formed outside of the emitter; a first doped region of the first conductivity type formed at a facet point between the intrinsic base region and one of the extrinsic base regions; a second doped region of said first conductivity type contained at the oute

Abstract: A method of dissipating charge from a substrate of an SOI device is provided wherein a charge dissipation path is formed in the device so that it abuts the various layers thereof. Exemplary charge dissipation paths include high conductive materials, resistive means, and field emission or arc discharge means. SOI structures having said charge dissipation path formed therein are also provided. SOI ESD circuits between SOI substrate and chip ground Vss are provided herein.

Abstract: An integrated circuit interconnect level capacitor is disclosed. In an exemplary embodiment, the capacitor includes a first insulator layer overlying an interconnect level surface of a semiconductor substrate having active devices. First and second conductive lines are provided in the first insulator layer and are separated by a trench defined by the first insulator layer and by sidewalls of the first and second conductive lines. A first conductive barrier layer overlies and connects the first and second conductive lines, and a second insulator layer overlies the first conductive barrier layer. A second conductive barrier layer overlies the second insulator layer, and a third conductive line is disposed in the trench and overlies the second conductive barrier layer.

Abstract: A magneto-resistive read head having a “parasitic shield” in a data storage system provides an alternative path for currents associated with sparkovers, thus preventing such currents from damaging the read head. The parasitic shield is provided in close proximity to a conventional magnetic shield. The electrical potential of parasitic shield is held essentially equal to the electrical potential of the sensor element. If charges accumulate on the conventional shield, current will flow to the parasitic shield at a lower potential than would be required for current to flow between the conventional shield and the sensor element. Alternatively, conductive spark gap devices are electrically coupled to sensor element leads and to each magnetic shield. Each spark gap device is brought within very close proximity of the substrate to provide an alternative path for charge that builds up between the sensor element and the substrate to be discharged.

Abstract: A method and structure for improving the latch-up characteristic of semiconductor devices is provided. A dual depth STI is used to isolate the wells from each other. The trench has a first substantially horizontal surface at a first depth and a second substantially horizontal surface at a second depth which is deeper than the first depth. The n- and p-wells are formed on either side of the trench. A highly doped region is formed in the substrate underneath the second substantially horizontal surface of the trench. The highly doped region abuts both the first and the second wells and extends the isolation of the trench.