Abstract: A thin film slider with an on-board multi-layer integrated circuit includes a substrate with an air bearing surface and a substantially parallel upper surface spanned by a deposit end. A magnetic head being formed at the deposit end, positioned to magnetically exchange data with a magnetic recording medium that passes beneath the air bearing surface. The upper surface bears an integrated multi-layer accessory circuit, which may be prepared using the CUBE process. Hence, components and vias of the different circuit layers are attached by interconnections that span the edges of the circuit layers. The accessory circuit preferably includes one or more memory devices, such as a cache memory, a DRAM circuit, an EPROM circuit, or another memory circuit appropriate to the application. In embodiments where the magnetic head is a magnetoresistive ("MR") head, the accessory circuit may also include a pre-amplifier and a sensing circuit to support operation of the MR head.

Abstract: An MR head receives ESD protection from a mechanism that automatically and releasably shorts the MR head whenever a suspension assembly on which the head is mounted is not installed in an HDA. The suspension assembly includes a flexure underlying a load beam, which is connected to an actuator arm. The MR head is mounted to a distal end of the flexure, leads from components of the MR head being brought out in the form of MR wire leads running along the load beam and the support arm to a nearby terminal connecting side tab. The conductors are separated and exposed at a designated point along the flexure to provide a contact region. A shorting bar, which comprises an electrically conductive member attached to the actuator arm, automatically connects the MR wire leads at the contact region when absence of support for the MR head permits the load beam to bend sufficiently toward the shorting bar.

Abstract: Interchip and intrachip electrical discharge suppression connections or networks are disclosed for three-dimensional multichip semiconductor structures. The interchip suppression networks electrically intercouple the power planes of the semiconductor device chips in the structure. This, in combination with conventional intrachip suppression networks present on the external connects or input/output pins of the individual chips in the structure, provides complete power plane-to-power plane, external connect-to-power plane and external connect-to-external connect protection against electrical discharge events, such as an electrostatic discharge occurring during handling and testing of the structure. The interchip electrical discharge suppression networks can be placed on an end layer or end semiconductor chip of the three-dimensional multichip semiconductor structure and connect to individual chips in the structure via an edge surface metallization.

Abstract: A fabrication method and resultant monolithic electronic module comprising a plurality of stacked planar extending arrays of integrated circuit chips. The fabrication method includes dicing a wafer of integrated circuit chips into a plurality of arrays of integrated circuit chips. The arrays of integrated circuit chips are then stacked to form an electronic module. A metallization pattern may be deposited on a substantially planar surface of the electronic module, and used to interconnect the various arrays of integrated circuit chips contained therein. Specific details of the fabrication method and resultant multi-chip package are set forth.

Abstract: A fabrication method and resultant electronic module having one or more surfaces enhanced with interconnects and components. Electronic modules having, for example, resistors and capacitors integral with a side surface thereof are disclosed. Further described are electronic modules with interconnects electrically attaching for example, side to side, or side to end surfaces are described. Moreover, discussion of an electronic module having a Silicon Front Face chip is contained herein. Specific details of the fabrication method, resulting electronic module, and related wafer processing are set forth.

Abstract: An MR head receives ESD protection from a mechanism that automatically and releasably shorts the MR head whenever a suspension assembly on which the head is mounted is not installed in an HDA. The suspension assembly includes a flexure underlying a load beam, which is connected to an actuator arm. The MR head is mounted to a distal end of the flexure, leads from components of the MR head being brought out in the form of MR wire leads running along the load beam and the support arm to a nearby terminal connecting side tab. The conductors are separated and exposed at a designated point along the flexure to provide a contact region. A shorting bar, which comprises an electrically conductive member attached to the actuator arm, automatically connects the MR wire leads at the contact region when absence of support for the MR head permits the load beam to bend sufficiently toward the shorting bar.