Abstract: A power converter operates in continuous conduction mode and outputs a regulated output voltage. A feedback-derived signal is used to regulate the output voltage. The feedback-derived signal is sampled at multiple time points during an OFF cycle of a power switch. A current-sense signal is also sampled at one or more time points during an ON cycle of the power switch. The current-sense signal is indicative of an output inductor current of the power converter. A calibrated feedback-derived voltage is then generated based on the multiple voltage samples of the feedback-derived signal and the one or more voltage samples of the current-sense signal. The calibrated feedback-derived voltage is less sensitive to an output inductor current loop resistance than the original voltage samples of the feedback-derived signal. The calibrated feedback-derived voltage also compensates for the nonlinearity of a diode of the output inductor current loop.

Abstract: A power converter having a switched capacitor buck/boost operation has first and second switches coupled to a first switching node, third and fourth switches coupled to a second switching node, a capacitor coupled between the first and second switching nodes, and an inductor coupled to the first switching node. A switch controller controls the switches to operate in voltage step-down mode and voltage step-up mode depending on a difference between converter output voltage VOUT and converter input voltage VIN. In a buck-optimized topology operating in a step-down mode, an output current flowing through the first switching node flows through only one switch at a given time. In a boost-optimized topology operating in a step-up mode, an output current flowing through the first switching node flows through only one switch at a given time. As a result, a more compact and efficient power converter may be realized at lower cost.

Abstract: Techniques for near zero light-load supply current in switching regulators are described. In one aspect a voltage regulator operating a normal mode is generating an error signal indicating a difference between the output and the regulated voltage. A control signal, at least in part based on the error signal, actively controls the output of the regulator. The control signal is monitored over period of time. The monitoring activates a signal indicating when the control signal is inactive for the period of time indicating a light-load condition. The voltage regulator is then placed in a standby mode when the signal is active and the error signal indicates the output is substantially at the regulated voltage. Portions of the voltage regulator are then disabled permitting the voltage regulator to operate at the minimum current draw.

Abstract: An integrated circuit includes a buck converter controller, a PFET, an NFET that is coupled in common drain configuration to the PFET, a first microbump that is connected to the source of the PFET, a second microbump that is connected to the source of the NFET, a third microbump that is connected to the common drain node, a fourth microbump that is connected to a feedback input lead of the controller, and a plurality of other microbumps. The other microbumps are utilized to supply signals to and/or to conduct signals from the controller. A respective one of the four microbumps is disposed to occupy a respective one of the four corners of a square pattern. The other microbumps are disposed in a regular grid along with the four microbumps, but none of the other microbumps is disposed between any two of the four microbumps.

Abstract: An Analog Tile Selection, Placement, Configuration and Programming (ATSPCP) tool communicates a power management characteristic query over a network. The query is displayed to a user on a webpage. The query is a solicitation for desired characteristics of a Power Management Integrated Circuit (PMIC). After receiving user requirements in a response to the query, the tool selects a number of power management integrated circuit tiles having pre-defined physical structures. The pre-defined structure of each tile includes a bus portion and a memory structure for storing configuring information for the tile. When combined in a Multi-Tile Power Management Integrated Circuit (MTPMIC), the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC that meets the user requirements. The ATSPCP tool combines the physical layout data of each selected PMIC tile to form composite physical layout data for the overall MTPMIC.

Abstract: A programmable analog tile integrated circuit is configured over a standardized bus by communicating tile configuration information from a first integrated circuit tile, through a second integrated circuit tile, to a third integrated circuit tile. Each of the three integrated circuit tiles is part of an integrated circuit. The standardized bus is formed when the tiles are placed adjacent one another. Data bus and control signal conductors of the adjacent tiles line up and interconnect such that each signal conductor is electrically connected to every tile. Tile configuration information may be written to a selected register identified by an address in any selected one of the tiles using the data bus and control lines, regardless of the relative physical locations of the tile sending and the tile receiving the information. Thus, tile configuration information may pass from one tile to another tile, through any number of intermediate tiles.

Abstract: A programmable analog tile integrated circuit configuration tool communicates a power management control characteristic query soliciting control requirement information for a novel Power Management Integrated Circuit (PMIC) tile in a Multi-Tile Power Management Integrated Circuit (MTPMIC). The configuration tool receives a user response to the query indicating control requirements across a network. The PMIC tile includes configuration registers. Configuration information bit values stored in the configuration registers control the operational characteristics of the functional circuitry of the tile. The configuration registers of each novel PMIC tile are accessible at pre-defined addresses on a standardized bus of the MTPMIC. In response to the user response, the configuration tool generates appropriate tile configuration information for loading the configuration registers such that the PMIC tile within the MTPMIC is programmed to satisfy the user's control requirements.

Abstract: A programmable analog tile integrated circuit placement tool allows a user to manipulate a graphical representation of a first power management integrated circuit (PMIC) tile with respect to a graphical representation of a second PMIC tile in a proposed Multi-Tile Power Management Integrated Circuit (MTPMIC). The novel PMIC tiles have pre-defined physical structures including a bus portion and a memory structure for storing configuration information for configuring the tile. When appropriately placed in a MTPMIC, the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC. A remote user with minimal training in analog circuit design may command the placement of individual tiles in a proposed MTPMIC layout. Upon receiving a user response indicating satisfaction with the placement of PMIC tiles, the tool quickly and automatically generates physical layout data suitable for fabrication of the MTPMIC.

Abstract: A programmable analog tile integrated circuit programming tool communicates a power management control characteristic query soliciting control requirement information for a novel power management integrated circuit (PMIC) tile in a multi-tile power management integrated circuit (MTPMIC). The programming tool receives a user response to the query indicating control requirements across a network. The novel PMIC tiles have a pre-defined physical structure including all memory structures required for configuration of each tile and a bus portion. When combined in a multi-tile power management integrated circuit (MTPMIC), the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC. The memory structure of each tile is individually addressable via the standardized bus. Thus, in response to control requirements, the programming tool programs a PMIC tile that is part of a MTPMIC to meet the control requirements.

Abstract: A power converter having a switched capacitor buck/boost operation has first and second switches coupled to a first switching node, third and fourth switches coupled to a second switching node, a capacitor coupled between the first and second switching nodes, and an inductor coupled to the first switching node. A switch controller controls the switches to operate in voltage step-down mode and voltage step-up mode depending on a difference between converter output voltage VOUT and converter input voltage VIN. In a buck-optimized topology operating in a step-down mode, an output current flowing through the first switching node flows through only one switch at a given time. In a boost-optimized topology operating in a step-up mode, an output current flowing through the first switching node flows through only one switch at a given time. As a result, a more compact and efficient power converter may be realized at lower cost.

Abstract: A comparing circuit and a control loop are used to maintain the peak level of current flowing through an inductor of a flyback converter. An inductor switch control signal controls an inductor switch through which the inductor current flows. The inductor current increases at a ramp-up rate during a ramp time and stops increasing at the end of the ramp time. The comparing circuit generates a timing signal that indicates a target time at which the inductor current would reach a predetermined current limit if the inductor current continued to increase at the ramp-up rate. The control loop then receives the timing signal and compares the target time to the end of the ramp time. The pulse width of the inductor switch control signal is increased when the target time occurs after the end of the ramp time. Adjusting the pulse width controls the peak of the inductor current.

Abstract: Techniques for near zero light-load supply current in switching regulators are described. In one aspect a voltage regulator operating a normal mode is generating an error signal indicating a difference between the output and the regulated voltage. A control signal, at least in part based on the error signal, actively controls the output of the regulator. The control signal is monitored over period of time. The monitoring activates a signal indicating when the control signal is inactive for the period of time indicating a light-load condition. The voltage regulator is then placed in a standby mode when the signal is active and the error signal indicates the output is substantially at the regulated voltage. Portions of the voltage regulator are then disabled permitting the voltage regulator to operate at the minimum current draw.

Abstract: Techniques for near zero light-load supply current in switching power supply are described. In one embodiment, a switching power supply comprises sub-circuits, a capacitor/inverter circuit, and a standby control circuit. The sub-circuits comprise a feedback resistor that supplies a fraction of an output voltage of the power supply, an integrator that provides an integrator output, a comparator that provides a pulse width modulated signal, a switching element that receives the pulse width modulated signal and modulates current such that the power supply provides a regulated voltage, and a monitoring circuit that provides a logic low signal when the pulse width modulated signal is absent over a period of time. The standby control circuit disables the sub-circuits when the logical low signal is detected permitting the switching power supply to operate at a minimum current, an re-enables the sub-circuits when an out of regulation signal from the capacitor/inverter circuit is detected.

Abstract: A comparing circuit and a control loop are used to maintain the peak level of current flowing through an inductor of a flyback converter. An inductor switch control signal controls a switch through which the inductor current flows. The inductor current increases at a ramp-up rate during a ramp time and stops increasing at the end of the ramp time. The comparing circuit generates a timing signal that indicates a target time at which the inductor current would reach a predetermined current limit if the inductor current continued to increase at the ramp-up rate. The control loop then receives the timing signal and compares the target time to the end of the ramp time. The pulse width of the inductor switch control signal is increased when the target time occurs after the end of the ramp time. Adjusting the frequency and pulse width controls the peak of the inductor current.

Abstract: A primary side controlled power converter having a voltage sensing means coupled to a transformer of the power converter and configured to provide a voltage feedback waveform representative of an output of the transformer is provided. A primary switching circuit operates to control energy storage of a primary side of the transformer. The primary switching circuit is operable during an on time and inoperable during an off time. The on and off time is switched at a system frequency. A feedback amplifier generates an error signal indicative of a difference between the voltage feedback waveform and a reference voltage. A sample and hold circuit samples the error signal at a periodic frequency during the off time. An error signal amplifier is configured to provide the sampled value to the primary switching circuit wherein the primary switching circuit controls the transformer and thereby regulates an output of the power converter.

Abstract: A power converter operates in continuous conduction mode and outputs a regulated output voltage. A feedback-derived signal is used to regulate the output voltage. The feedback-derived signal is sampled at multiple time points during an OFF cycle of a power switch. A current-sense signal is also sampled at one or more time points during an ON cycle of the power switch. The current-sense signal is indicative of an output inductor current of the power converter. A calibrated feedback-derived voltage is then generated based on the multiple voltage samples of the feedback-derived signal and the one or more voltage samples of the current-sense signal. The calibrated feedback-derived voltage is less sensitive to an output inductor current loop resistance than the original voltage samples of the feedback-derived signal. The calibrated feedback-derived voltage also compensates for the nonlinearity of a diode of the output inductor current loop.

Abstract: A comparing circuit and a control loop are used to maintain the peak level of current flowing through an inductor of a flyback converter. An inductor switch control signal controls a switch through which the inductor current flows. The inductor current increases at a ramp-up rate during a ramp time and stops increasing at the end of the ramp time. The comparing circuit generates a timing signal that indicates a target time at which the inductor current would reach a predetermined current limit if the inductor current continued to increase at the ramp-up rate. The control loop then receives the timing signal and compares the target time to the end of the ramp time. The pulse width of the inductor switch control signal is increased when the target time occurs after the end of the ramp time. Adjusting the frequency and pulse width controls the peak of the inductor current.

Abstract: Techniques for near zero light-load supply current in switching regulators are described. In one aspect a voltage regulator operating a normal mode is generating an error signal indicating a difference between the output and the regulated voltage. A control signal, at least in part based on the error signal, actively controls the output of the regulator. The control signal is monitored over a period of time. The monitoring activates a signal indicating when the control signal is inactive for the period of time indicating a light-load condition. The voltage regulator is then placed in a standby mode when the signal is active and the error signal indicates the output is substantially at the regulated voltage. Portions of the voltage regulator are then disabled permitting the voltage regulator to operate at the minimum current draw.

Abstract: A single terminal is used to configure an integrated circuit into one of three states. A circuit within the integrated circuit is coupled to the terminal and determines whether the terminal: 1) is coupled by a low impedance to a voltage source, or 2) is coupled by a medium impedance to the voltage source, or 3) is floating or substantially floating. The circuit asserts a first digital logic signal when the circuit determines that the terminal is coupled by the low impedance to the voltage source. The circuit asserts a second digital logic signal when the circuit determines that the terminal is coupled by the medium impedance to the voltage source. The circuit asserts a third digital logic signal when the circuit determines that the terminal is floating or substantially floating. The terminal and circuit are particular suited for use in a Power Management Unit (PMU) Integrated Circuit.

Abstract: A self-oscillating flyback converter includes a controller integrated circuit housed in a 3-pin package. A switch control terminal is coupled to the base of an inductor switch that controls the current through a primary inductor of the converter. The controller IC adjusts the on time of the switch such that output current remains constant in constant current mode and output voltage remains constant in constant voltage mode. A signal received on a switch control terminal turns the switch off and provides an indication of the output current when the switch is on. A signal received on a feedback terminal powers the controller IC and provides an indication of the output voltage when the switch is off. The controller IC is grounded through a ground terminal. The flyback converter transitions from critical conduction mode to discontinuous conduction mode at light loads to prevent its efficiency from deteriorating at high switching frequencies.