Abstract: A circuit for shifting bussed data includes a first column of shift blocks, a compare block, and a second column of multiplexer blocks. The first column shifts the bussed data by a number of bits specified by first bits of a shift control input. The compare block determines the value of a second bit of the shift control input and creates an output reflecting that value. The second column has a control input coupled to the output of the compare block, shifts the data by one byte when the second bit of the shift control input has a first value, and does not shift the data when the second bit has a second value. The shift, compare, and multiplexer blocks can be substantially similar logic blocks programmable to perform any of these functions, can include N-bit data inputs and outputs, and can operate on the bussed data as an N-bit bus.

Abstract: An apparatus includes an integrated circuit with a clock network in an array of circuit blocks. The clock network includes routing tracks, distribution spines, and clock leaves. The routing tracks and the distribution spines are bidirectional.

Abstract: A method and apparatus to test the inter-die interface between two or more semiconductor die in die stacking applications, where a mismatch exists between the number of input and output pads on a base die and the number of input and output pads on a stacked die. In a first embodiment, a number of through-die vias (TDVs) may be used to implement inter-die signal paths using standard or flexible design rules to maintain statistical TDV yield despite the lack of continuity verification of the inter-die signals paths. In alternate embodiments, programmable multiplexers may be utilized to share one or more inter-die connections between the base die and the one or more stacked die so as to facilitate testing and normal operation of each inter-die connection. In other embodiments, spare TDVs are utilized only during test operations, so as to accommodate the mismatch.

Abstract: In an apparatus, an interconnect block includes a plurality of configuration memory cells. A plurality of multiplexers is respectively coupled to the configuration memory cells. An acknowledge circuit is coupled to the configuration memory cells. The acknowledge circuit includes a plurality of acknowledge inputs. The configuration memory cells are coupled to selectively set states of the plurality of multiplexers and correspondingly selectively activate inputs of the plurality of acknowledge inputs. A data ready circuit is coupled to at least one multiplexer output of the plurality of multiplexers.

Abstract: An apparatus includes a first output stage and a first input stage of a first single track buffer, as well as a second output stage and a second input stage of a second single track buffer. The second single track buffer is downstream from the first single track buffer. The first output stage and the second input stage are coupled to one another via bidirectional rails. The first output stage and the second input stage in combination provide a first pulse generator.

Abstract: A wheel suspension system for a three-wheeled motorcycle or “trike” includes parallel wheels mounted on vertically pivoting suspension arms governed by hydraulic pistons. The pistons have upper liquid reservoirs that are interconnected through a valve system, which interconnects the upper reservoirs when the trike is in motion, allowing opposing vertical wheel movements when banking through turns, and prevents liquid exchange when the trike is stopped, thereby holding the motorcycle upright, Embodiments include a manual and/or automatic valve control. A threshold switching speed for an automatic controller can be factory set and/or user adjustable. The pistons can include directly interconnected lower fluid reservoirs. A shock-absorbing reservoir can allow transient vertical movement of both wheels to absorb shocks. A cover system can emulate the appearance of saddle bags and can appear to be covering only a single wheel.

Abstract: Multiplier circuits that can optionally be configured as bit shifters. An exemplary multiplier includes a one-hot circuit, a multi-bit multiplexing circuit, and a multiply block. The one-hot circuit has a multi-bit input and a multi-bit output. The multiplexing circuit has first and second multi-bit inputs and a multi-bit output, with the first input of the multiplexing circuit being coupled to the output of the one-hot circuit. The multiply block has first and second multi-bit inputs and a multi-bit output, with the first input of the multiply block being coupled to the output of the multiplexing circuit. When selected by the multiplexer, the position of the single high bit in the one-hot circuit output determines the number of bits by which the multiplier output is shifted relative to the second multiplier input. When the one-hot circuit output is not selected as an input to the multiplier, the multiplier performs a multiply function.

Abstract: A wheel suspension system for a three-wheeled motorcycle or “trike” includes parallel wheels mounted on vertically pivoting suspension arms governed by hydraulic pistons. The pistons have upper liquid reservoirs that are interconnected through a valve system, which interconnects the upper reservoirs when the trike is in motion, allowing opposing vertical wheel movements when banking through turns, and prevents liquid exchange when the trike is stopped, thereby holding the motorcycle upright, Embodiments include a manual and/or automatic valve control. A threshold switching speed for an automatic controller can be factory set and/or user adjustable. The pistons can include directly interconnected lower fluid reservoirs. A shock-absorbing reservoir can allow transient vertical movement of both wheels to absorb shocks. A cover system can emulate the appearance of saddle bags and can appear to be covering only a single wheel.

Abstract: A wheel suspension system for a three-wheeled motorcycle or “trike” includes parallel wheels mounted on vertically pivoting suspension arms governed by hydraulic pistons. The pistons have upper liquid reservoirs that are interconnected through a valve system, which interconnects the upper reservoirs when the trike is in motion, allowing opposing vertical wheel movements when banking through turns, and prevents liquid exchange when the trike is stopped, thereby holding the motorcycle upright, Embodiments include a manual and/or automatic valve control. A threshold switching speed for an automatic controller can be factory set and/or user adjustable. The pistons can include directly interconnected lower fluid reservoirs. A shock-absorbing reservoir can allow transient vertical movement of both wheels to absorb shocks. A cover system can emulate the appearance of saddle bags and can appear to be covering only a single wheel.

Abstract: An embodiment of an integrated circuit (IC) is described. This embodiment of the IC includes an interposer; a first die on an interposer, where the first die generates a global signal propagated through the interposer; and a second die on the surface of the interposer and coupled to the global signal. The first die and the second die each is configured to implement a same operating state concurrently in response to the global signal.

Abstract: In a multiplier architecture, all stages of a multiplication function are implemented using a uniform array of logic blocks. An exemplary multiplier circuit includes a two-dimensional array of substantially similar logic blocks. Each logic block includes a multiply block and a logic circuit driven by the multiply block. The logic circuit is coupled to implement an add function. A first portion of the array is coupled to receive the first and second multiplicand inputs, to provide a partial product bus, and to provide lower bits of the product output. A second portion is coupled to receive the partial product bus from the first portion of the array, and to provide from the partial product bus upper bits of the product output. The multiply blocks may be non-uniform arrays, e.g., logical AND gates and full adders in all but one column, with only logical AND gates in the remaining column.

Abstract: A wheel suspension system for a three-wheeled motorcycle or “trike” includes parallel wheels mounted on vertically pivoting suspension arms governed by hydraulic pistons. The pistons have upper liquid reservoirs that are interconnected through a valve system, which interconnects the upper reservoirs when the trike is in motion, allowing opposing vertical wheel movements when banking through turns, and prevents liquid exchange when the trike is stopped, thereby holding the motorcycle upright, Embodiments include a manual and/or automatic valve control. A threshold switching speed for an automatic controller can be factory set and/or user adjustable. The pistons can include directly interconnected lower fluid reservoirs. A shock-absorbing reservoir can allow transient vertical movement of both wheels to absorb shocks. A cover system can emulate the appearance of saddle bags and can appear to be covering only a single wheel.

Abstract: Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each slice includes a mode port that receives mode control signals for dynamically altering the function and connectivity of related slices. Such alterations can occur with or without reconfiguring the PLD.

Abstract: An apparatus for error checking is described. The apparatus includes a matrix having a plurality of bit position columns and rows, where the bit position columns are equal in number to data bits of a word length, the word length for a word serial transmission of a data vector, where the bit position columns are one each for each data bit. The bit position rows are equal in number to syndrome bits, and the bit position rows are one each for each syndrome bit. A portion of the bit position columns are allocated to parity bits for a selected word of the data vector, where the portion of the bit position columns for the selected word are one each for each parity bit allocated to the selected word.

Abstract: An embodiment of a method to form a hybrid integrated circuit device is described. This embodiment of the method comprises: forming a first die using a first lithography, where the first die is on a substrate; and forming a second die using a second lithography, where the second die is on the first die. The first lithography used to form the first die is a larger lithography than the second lithography used to form the second die. The first die is an IO die.

Abstract: Method and apparatus for error checking information is described. Configuration data includes data bits and parity bits. Notably, parity bits may be relocated for determining a syndrome value. Syndrome bits are determined by computing a partial syndrome value for each word serially transmitted of the configuration data, where the configuration data includes one or more data vectors. Location of each word of the configuration data is identified. It is determined whether a partial syndrome value is an initial partial syndrome value or other partial syndrome value responsive to word location. An initial partial syndrome value is stored, and subsequent partial syndrome values are cumulatively added for each word of a data vector to arrive at a syndrome value for the data vector.

Abstract: A programmable integrated circuit (IC) with mirrored interconnect structure. The IC includes a plurality of arrangements, which are horizontally arranged. Each arrangement includes a first logic column, an interconnect column, and a second logic column. Each interconnect column includes programmable interconnect blocks (148), and each of the first and second logic columns includes programmable logic blocks. Each programmable interconnect block provides a plurality of first input and output ports on a first side and a plurality of second input and output ports on a second side. The first ports and the first side of each of the programmable interconnect blocks physically mirror the second ports and the second side of the programmable interconnect block. The ports of the programmable interconnect blocks are coupled to the ports of the programmable logic blocks in the first and second logic columns.

Abstract: An embodiment of an integrated circuit (IC) is described. This embodiment of the IC includes an interposer; a first die on an interposer, where the first die generates a global signal propagated through the interposer; and a second die on the surface of the interposer and coupled to the global signal. The first die and the second die each is configured to implement a same operating state concurrently in response to the global signal.

Abstract: A method of configuring an integrated circuit (IC) can include receiving configuration data within a master die of the IC. The IC can include the master die and a slave die. A master segment and a slave segment of the configuration data can be determined. The slave segment of the configuration data can be distributed to the slave die of the IC.

Abstract: Circuits and methods for facilitating distribution of gated clocks in a programmable integrated circuit such as a field programmable gate array (FPGA) are described. Dynamic power savings are achieved in a FPGA by providing gated clock driver circuitry at various places in a hierarchical clock distribution network. The gated clock circuitry provides a clock signal gated by an enable signal to clocked elements. Configurable logic blocks (CLBs) comprising the clocked elements and programmable interconnect tiles are disposed in the gate array. Clock signals are distributed to the CLBs via a clock distribution network. Clock enable signals are provided corresponding to some of the clock signals. Clock buffers or drivers are provided within the clock distribution network that drive gated clock signals to CLBs. By disabling certain clocked elements using one or more embodiments of the invention when portions of the FPGA are inactive, dynamic power consumption is reduced.