Abstract: A bus-based logic block in a self-timed integrated circuit includes N first input multiplexers, N second input multiplexers, and N lookup tables, N being greater than one. The select inputs of all N first input multiplexers are coupled together, and the select inputs of all N second input multiplexers are coupled together. A corresponding data input of each first input multiplexer is one bit of a first self-timed N-bit bus, and a corresponding data input of each second multiplexer is one bit of a second self-timed N-bit bus. Each lookup table has first and second inputs coupled to the outputs of the first and second input multiplexers. Corresponding control inputs of all N lookup tables are coupled together. Thus, all operations are performed on one or more N-bit self-timed busses, rather than on individual data signals.

Abstract: A multi-mode circuit for a self-timed integrated circuit is provided. The multi-mode circuit is programmable to operate in two or more modes, and is coupled to require, in each mode, receipt of a token on at least one of first, second, or third inputs before providing an output token. The multi-mode circuit is further coupled to require tokens on different inputs in at least two different modes. The multi-mode circuit can be an output circuit for a logic block in an integrated circuit including an array of interconnected logic blocks, where each logic block includes a logic circuit and a multi-mode circuit. One input of each multi-mode circuit can be programmably coupled to a select output of a multi-mode circuit in an adjacent logic block. Based on the programmed mode and the tokens received, the circuit routes data between inputs and outputs of the circuit.

Abstract: Circuits for merging data streams in a self-timed programmable integrated circuit. A programmable integrated circuit includes interconnected logic blocks, each including a logic circuit and an output multiplexer circuit including an arbiter and a multiplexer. Each arbiter is coupled to receive ready signals provided with first and second outputs of the logic circuit. Each multiplexer has first and second data inputs coupled to the outputs of the logic circuit, a select input programmably coupled, in one of a plurality of operating modes, to an arbiter output, and a data output coupled to an output of the logic block. The output multiplexer circuit provides an output token only when a first token indicates valid new data on the arbiter output and a second token indicates valid new data on one of the data inputs, and stores a third token received on the other data input until the other data input is selected by the multiplexer.

Abstract: Methods of initializing an integrated circuit (IC) in which the routing structures have data lines and handshake circuitry are provided. A node of each of the data lines is driven to a predetermined value, and the handshake circuit is disabled by disabling an acknowledge path within the handshake circuitry, e.g., by forcing all acknowledge signals in the acknowledge path to signal an acknowledgement of received data. The disablement causes the predetermined value to propagate throughout the data lines. The handshake circuitry is then enabled by enabling the acknowledge path, which releases the data lines to assume values determined by operation of the IC. When the IC is a programmable IC, configuration values may be programmed into the IC after disabling the acknowledge path and before enabling the handshake circuitry. When the handshake circuitry is enabled, the data lines assume initial values determined by the programmed configuration values.

Abstract: An exemplary circuit for implementing conditional statements in self-timed logic circuits includes first and second logic circuits, an input circuit, an output circuit, and a pipelined routing path. The first and second logic circuits each have a self-timed input and a self-timed output. The input circuit is coupled to provide a self-timed input signal to the self-timed input of a selected one of the first or second logic circuits based on the value of a control signal, and is further coupled to output a self-timed select signal. The output circuit is coupled to receive the self-timed output from the first logic circuit and the self-timed output from the second logic circuit, and to output a selected one of the self-timed outputs based on a value of the self-timed select signal. The pipelined routing path routes the self-timed select signal from the input circuit to the output circuit.

Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.

Abstract: Integrated circuits (ICs) having bus-based programmable interconnect structures are provided. An IC includes substantially similar logic blocks and a programmable interconnect structure programmably interconnecting the logic blocks. The programmable interconnect structure includes bus structures and programmable switching structures programmably interconnecting the bus structures. Each bus structure includes N data lines, where N is an integer greater than one, and N commonly controlled storage elements (e.g., latches) for storing data on the N data lines. In some embodiments, at least one of the bus structures includes handshake logic, including a C-element coupled to drive a ready line, to receive an acknowledge line, and to provide a control signal to each of the N storage elements in the bus structure.

Abstract: Signal distribution of a regional signal is described. An integrated circuit includes a global signal distribution network, a regional signal distribution network and a regional buffer. The regional buffer has an output coupled at an end of the regional signal distribution network. The regional signal distribution network is coupled to a configurable logic block via an interconnect tile. The regional buffer is coupled to a regional clock capable input/output block. Additionally described is a source synchronous interface for regional signal distribution.

Abstract: Integrated circuits (ICs) having novel handshake logic are provided. An IC includes a ready multiplexer, an acknowledge demultiplexer, a C-element coupled to the ready multiplexer and the acknowledge demultiplexer, a logic gate, and a storage element (e.g., a latch). The logic gate has a first input coupled to a control output of the C-element, and a second input. The storage element includes a data multiplexer and a latch. The data multiplexer has M data inputs coupled to data inputs of the storage element, a select input coupled to the output of the logic gate, and a data output, M being an integer greater than one. The latch has a data input coupled to the data output of the first data multiplexer and an output coupled to an output of the storage element. The logic gate can be a logical AND gate with the second input coupled to a memory cell.

Abstract: In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer and each slice has a direct connection to an adjoining slice; and means for configuring the plurality of digital signal processing slices to perform one or more mathematical operations, via, for example, opmodes. This IC allows for the implementation of some basic math functions, such as add, subtract, multiply and divide. Many other applications may be implemented using the one or more DSP slices, for example, accumulate, multiply accumulate (MACC), a wide multiplexer, barrel shifter, counter, and folded, decimating, and interpolating FIRs to name a few.

Abstract: An FPGA is laid out as a plurality of repeatable tiles, wherein the tiles are disposed in columns that extend from one side of the die to another side of the die, and wherein each column includes tiles primarily of one type. Because substantially all die area of a column is due to tiles of a single type, the width of the tiles of each column can be optimized and is largely independent of the size of the other types of tiles on the die. The confines of each type of tile can therefore be set to match the size of the circuitry of the tile. Rather than providing a ring of input/output blocks (IOBs) around the die periphery, IOB tiles are disposed in columns only. Where more than two columns worth of IOBs is required, more than two columns of IOB tiles can be provided.

Abstract: Formation of a hybrid integrated circuit device (400) is described. A design for the integrated circuit (100) is obtained and separated into at least two portions responsive to component sizes. A first die (200) is formed for a first portion of the hybrid integrated circuit device (400) using at least in part a first minimum dimension lithography. A second die (300) is formed for a second portion of the device using at least in part a second minimum dimension lithography, where the second die (300) has the second minimum dimension lithography as a smallest lithography used for the forming of the second die (300). The first die (200) and the second die (300) are attached to one another via coupling interconnects respectively thereof to provide the hybrid integrated circuit device (400).

Abstract: Structures and methods of avoiding hold time violations in a design implemented in a PLD. In a programmable device, the delay of a signal path varies, e.g., depending on the separation between the source and destination of the signal. An optional delay element is provided between a programmable interconnect structure and a destination logic element having a clock skew relative to the source. The optional delay element is programmed by the implementation software to introduce a delay on the signal path when necessary to meet the hold time requirements for the destination logic element. The optional delay is designed to be large enough to overcome hold-time violations even for the largest possible clock skew and the smallest possible signal delay. When no hold time violation occurs, the optional delay element is configured to bypass the additional delay, to avoid imposing a large setup requirement on the signal.

Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.

Abstract: A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a plurality of switches coupling the main trunk to the plurality of branches.

Abstract: Methods of manufacturing a family of packaged integrated circuits (ICs) having at least two different logic capacities. A first IC die includes two different portions, of which at least one portion can be deliberately rendered non-operational in some manner (e.g., non-functional, inaccessible, and/or non-programmable) within the package. A first set of the first IC dies are packaged such that both portions of the dies are operational. A second set of the first IC dies are packaged such that only the first portion of each die is operational. Once the first and second sets are packaged and the second set of ICs has been evaluated, a decision is made whether or not to manufacture a second IC die that includes the first portion of the first die, while excluding the second portion.

Abstract: According to particular example embodiments, an integrated circuit includes one or more serializing data transmitters. Each such data transmitter is arranged to transmit data on a respective data output port of the integrated circuit, wherein the respective data output port for at least one of the data transmitters is dedicated to transmitting periodic data used for clocking a respective target circuit. In other particular embodiments involving feedback, phase-locked loop (PLL) signal control and/or delay-locked loop (DLL) signal control is achieved in functional blocks of a programmable logic device (PLD). The PLD is responsive to a source clock and includes a configurable logic array that includes configurable logic blocks and configurable routing blocks, and the respective data output port for at least one of the data transmitters provides a respective target clock.

Abstract: An integrated circuit die (e.g., a programmable logic device (PLD) die) is manufactured that has the capability of being configured as at least two differently-sized family members. The IC die is tested prior to packaging. If a first portion of the IC die is fully functional, but a second portion includes a localized defect, then the IC die is packaged with a product selection code that configures the IC die to operate as only the first portion of the die. The second portion of the die is deliberately rendered non-operational. Therefore, the IC die can still be sold as a fully functional packaged IC.

Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.

Abstract: Described are arithmetic circuits divided logically into a product generator and an adder. Multiplexing circuitry logically disposed between the product generator and the adder supports conventional functionality by providing partial products from the product generator to addend terminals of the adder. The multiplexing circuitry can also be controlled to direct a number of external added inputs to the adder. The additional addend inputs can include inputs and outputs cascaded from other arithmetic circuits.