Abstract: Structures and methods of adding metal-to-metal capacitors to static memory cells to reduce susceptibility to SEUs. The addition of metal-to-metal capacitors is particularly suited to programmable logic devices (PLDs), because of the relatively large area required to implement an effective metal-to-metal capacitor, compared (for example) to the size of the static memory cell itself. The configuration memory cells of PLDs are typically placed next to other logic (e.g., the configurable elements controlled by the configuration memory cells) that can be overlain by the metal-to-metal capacitors. Therefore, metal-to-metal capacitors can be used in PLD configuration memory cells where they might be impractical in simple memory arrays. However, metal-to-metal capacitors can also be applied to integrated circuits other than PLDs.

Abstract: A memory includes a plurality of row segments, with each row segment having a number of memory cells coupled to a corresponding dataline segment pair. Dataline driver circuits are provided between row segments to buffer signals on adjacent dataline segments. A control circuit is coupled to at least one row segment, and provides control signals to the at least one row segment and to the dataline driver circuits.

Abstract: A programmable integrated circuit (IC) includes rows and columns of tiles, each tile including logic blocks, segments of interconnect lines, and programmable structures (e.g., routing multiplexers, input multiplexers). Some interconnect lines can be used to interconnect two programmable structures included in tiles located in different rows and different columns. Thus, these “diagonal” interconnect lines also have programmable access to other programmable interconnect lines (e.g., straight interconnect lines and/or other diagonal interconnect lines) in the general interconnect structure. In some embodiments, the diagonal interconnect lines include “doubles”, which interconnect programmable structures in tiles diagonally adjacent to one another, and “pents”, which interconnect programmable structures in tiles separated by two intervening rows (or columns) and one intervening column (or row).

Abstract: A programmable integrated circuit (IC) includes rows and columns of tiles, each tile including logic blocks, segments of interconnect lines, and programmable structures (e.g., routing multiplexers driving the interconnect lines, input multiplexers driving the logic blocks). The interconnect lines can be used, for example, to interconnect two programmable structures included in tiles located in different rows and different columns. Thus, these “diagonal” interconnect lines also have programmable access to other diagonal interconnect lines in the general interconnect structure. In some embodiments, the diagonal interconnect lines include “doubles”, which interconnect programmable structures in tiles diagonally adjacent to one another, and “pents”, which interconnect programmable structures in tiles separated by two intervening rows (or columns) and one intervening column (or row).

Abstract: In an integrated circuit including an array of substantially similar tiles, a tile includes a logic block and at least one column of routing multiplexers driving interconnect lines that can be used to programmably interconnect the logic blocks. An output terminal of the logic block drives a vertically adjacent subset of the routing multiplexers in the column. Optionally, the tile also includes a second column of routing multiplexers. The logic block output terminal also drives a vertically adjacent subset of the routing multiplexers in the second column, and in some embodiments the two subsets are physically located in horizontal alignment with one another within the tile. The tile can also include a column of input multiplexers for the logic block. The logic block output terminal also drives a vertically adjacent subset of the input multiplexers, and the subsets of routing multiplexers and input multiplexers can be horizontally aligned within the tile.

Abstract: A programmable logic block provides N-bit and M-bit (e.g., (N/2)-bit) lookahead functionality for carry chains traversing the logic block, N and M being integers greater than one. An exemplary programmable logic block includes four carry multiplexers that together form a 4-bit lookahead carry chain. The 4-bit lookahead carry chain also provides a 2-bit lookahead output after the second carry multiplexer. Alternatively, the last two bits of the 4-bit lookahead carry chain can be used as a 2-bit lookahead carry chain. In one embodiment, the programmable logic block also includes four function generators associated with the four carry multiplexers. Each function generator drives a select terminal of the associated carry multiplexer. The 4-bit and 2-bit carry chains can be programmably coupled to an interconnect structure of the PLD at the carry out output terminals. In some embodiments, an initialization value can also be provided to the 4-bit and 2-bit carry chains.

Abstract: A programmable lookup table optionally provides two input signals and two output signals to an interconnect structure of a programmable integrated circuit when programmed to function as a random access memory (RAM). An integrated circuit includes an interconnect structure and a N-input lookup table (LUT) having input and output terminals coupled to the interconnect structure. The LUT can be configured to function as a single-bit wide RAM (e.g., a (2**N)×1 RAM) having N input address signals coupled to the interconnect structure and one output signal coupled to the interconnect structure, or as a multi-bit wide RAM (e.g., a (2**(N?1))×2 RAM) having fewer than N (e.g., N?1) input address signals coupled to the interconnect structure and at least two output signals coupled to the interconnect structure. Optionally, the LUT can also be configured as shift register logic, e.g., a 2**(N?1)-bit shift register or two 2**(N?2)-bit shift registers.

Abstract: A programmable logic block provides programmable initialization values for carry chains traversing the logic block, without consuming user logic resources. An exemplary programmable logic block includes two or more carry multiplexers coupled together to form a carry chain for the programmable logic block. A carry initialization circuit has an output terminal coupled to a data input terminal of a first carry multiplexer in the carry chain. The carry initialization circuit is controlled by configuration memory cells of the programmable logic block to select one of a carry in signal, a power high signal, a ground signal, and (optionally) a signal from an interconnect structure of the logic block. Thus, an initialization value (e.g., power high or ground) can be provided to the carry chain without consuming other programmable resources within the logic block.

Abstract: A programmable integrated circuit (IC) provides high routing flexibility without the use of an output multiplexer structure. According to one embodiment, an IC includes programmable tiles arrayed in rows and columns. Output multiplexer structures are not included in the programmable tiles. Routing flexibility is provided in each tile by input multiplexers coupled between a general interconnect structure and the input terminals of a logic block, and by providing direct access from the logic block output terminals (e.g., lookup table outputs and memory element outputs) to both horizontal and vertical interconnect lines. In some embodiments, the logic block output signals can also drive “diagonal” interconnect lines in the general interconnect structure.

Abstract: According to one aspect of the invention, a circuit for accessing data in a memory is disclosed. The circuit generally comprises a first port having a read logic circuit and a first output which generates data from the memory. A second port has a read logic circuit and a write logic circuit. A second output is coupled to the second port, and also generates data from the memory. Circuits for separately selecting read and write widths for a port of a memory, such as a random access memory, are disclosed. Finally, other embodiments related to implementing a content addressable memory in a programmable logic device are disclosed. Further, a method of accessing data in a memory is disclosed.

Abstract: According to one aspect of the invention, a circuit for accessing data in a memory is disclosed. The circuit generally comprises a first port having a read logic circuit and a first output which generates data from the memory. A second port has a read logic circuit and a write logic circuit. A second output is coupled to the second port, and also generates data from the memory. Circuits for separately selecting read and write widths for a port of a memory, such as a random access memory, are disclosed. Finally, other embodiments related to implementing a content addressable memory in a programmable logic device are disclosed. Further, a method of accessing data in a memory is disclosed.

Abstract: In an integrated circuit including an array of substantially similar tiles, a tile includes a logic block and one or more columns of routing multiplexers driving interconnect lines that can be used to programmably interconnect the logic blocks. Each routing multiplexer in a first column drives a vertically adjacent subset of the routing multiplexers in the first and/or a second column. Optionally, each routing multiplexer also drives a vertically adjacent subset of a column of input multiplexers of a logic block. In some embodiments, the adjacent groups of routing multiplexers and input multiplexers driven by each routing multiplexer are horizontally aligned within the tile. In some embodiments, every signal coupled to drive one of the routing multiplexers in a column drives a vertically adjacent subset of the routing multiplexers. In some embodiments, each interconnect line has exit points, and every exit point drives a vertically adjacent set of the routing multiplexers.

Abstract: Efficient implementations of arithmetic functions in programmable ICs include carry chain multiplexers driven by dual-output programmable function generators. A function generator having two output signals is programmed to generate both an exclusive OR (XOR) function of first and second input signals and a second function. In some embodiments, the second function is simply the second input signal to the XOR function. In other embodiments, the second function is a different function optionally independent of the first and second input signals. The XOR function output drives the select terminal of a carry multiplexer, which selects between a carry in signal and one of the second input signal and the second function output signal to provide the carry out output signal. The sum or multiplier output value is provided by an XOR gate driven by the XOR function output and by the carry in signal, and can be optionally registered.

Abstract: A programmable logic block provides fast interconnect paths between carry multiplexer output terminals and the input terminals of function generators (e.g., lookup tables) in the same logic block. An integrated circuit includes an interconnect structure, a function generator, and a carry multiplexer having a select terminal programmably coupled to an output terminal of the function generator. An output signal from the carry multiplexer can traverse the interconnect structure to reach the input terminals of the function generator. However, a “fast connect” path is also provided that interconnects the carry multiplexer output with an input terminal of the function generator, without traversing the interconnect structure. In some embodiments, fast connect paths are also provided to input terminals of other function generators in the same logic block.

Abstract: A programmable logic block provides fast interconnect paths between memory element output terminals and the input terminals of carry multiplexers in the same logic block. An integrated circuit includes an interconnect structure, a function generator, a carry chain multiplexer coupled to an output terminal of the function generator, and a memory element programmably coupled to the output terminal of the function generator. An output signal from the memory element can traverse the interconnect structure to reach an input terminal of the carry multiplexer. However, a “fast connect” path is also provided that interconnects the memory element output with an input terminal of the carry multiplexer, without traversing the interconnect structure. In some embodiments, fast connect paths are also provided to the input terminals the function generator, and to the input terminals of other function generators and/or carry multiplexers in the same logic block.

Abstract: A programmable lookup table for an integrated circuit (IC) optionally provides two input signals and two output signals to an interconnect structure of the programmable IC when programmed to function as shift register logic. According to one embodiment, an integrated circuit includes an interconnect structure and a N-input lookup table (LUT) having input and output terminals coupled to the interconnect structure, where N is a integer. The LUT can be configured to function as a (2**(N?1))-bit shift register having a shift in input signal and one output signal coupled to the interconnect structure, or as a two (2**(N?2))-bit shift registers having two shift in input signals and two output signals coupled to the interconnect structure. In some embodiments, each bit of the shift register includes two memory cells of the LUT, a first memory cell functioning as a master latch and a second memory cell functioning as a slave latch.

Abstract: Efficient implementations of wide logic functions (e.g., priority encoders, AND gates, OR gates) in programmable ICs include carry chain multiplexers driven by dual-output programmable function generators. A function generator having two output signals is programmed to generate first and second function output signals. The first and second functions can optionally share some or all of the input signals. The first function output signal drives the select terminal of a carry multiplexer, which selects between a carry in input signal and the second function output signal to provide the carry out output signal. The wide function result is provided by the final carry multiplexer in a chain of such carry multiplexers. In an exemplary wide AND gate, the first function is an AND function, and the second function is ground. In an exemplary wide OR gate, the first function is a NOR function, and the second function is power high VDD.

Abstract: A programmable input structure for a logic block provides the capability of “bouncing” a logic block input signal back to the interconnect structure of the integrated circuit, and/or to other input terminals of the logic block, without disabling other functions in the logic block. A programmable input multiplexer circuit selects one of the available signals from the interconnect structure, and passes the selected interconnect signal to a logic block. The signal can be disabled within the logic block by programming a bounce multiplexer circuit to select a static value (e.g., power high or ground) instead of the selected interconnect signal. Therefore, the selected signal is safely provided to the interconnect structure and/or another input multiplexer circuit, in addition to the logic block input terminal.

Abstract: An interconnect structure in which “diagonal” and “straight” interconnect lines are interleaved to minimize coupling between adjacent interconnect lines. An interconnect structure for an integrated circuit comprises rows and columns of tiles. Interconnect lines extend at least in part along a first column of the tiles, the interconnect lines including straight and diagonal interconnect lines. A “straight” interconnect line interconnects at least two tiles in the first column, and a “diagonal” interconnect line interconnects a tile in the first column with at least one tile in a different column and row. The interconnect lines are laid out in parallel fashion such that no straight interconnect line is physically adjacent to more than one other straight interconnect line, and no diagonal interconnect line is physically adjacent to more than one other diagonal interconnect line. Optionally, no two physically adjacent interconnect lines drive in the same direction within the first column.

Abstract: A programmable input structure for a programmable logic circuit provides the capability of “fanning out” a selected signal to two or more input terminals of the programmable logic circuit, thereby increasing the routability of the logic block input signals. A logic block for an integrated circuit includes a programmable logic circuit and input multiplexers programmably selecting an input signal to provide to the programmable logic circuit. Also included in the integrated circuit are fan multiplexers that do not drive the programmable logic circuit directly. Instead, the fan multiplexers drive two or more of the input multiplexers that can, optionally, drive other input multiplexers in the same logic block, providing additional selection options among potential input signals. In some embodiments, the fan multiplexers are driven by global and/or regional clock signals. Thus, existing clock distribution structures can be used to provide high fanout input signals to the programmable logic circuit.