Abstract: The UTILITY RESOURCE ASSET MANAGEMENT SYSTEM APPARATUSES, METHODS AND SYSTEMS (“URAMS”) transform weather, terrain, and utility asset parameter data via URAMS components into damage predictions with confidence metrics, alerts, and asset allocation and response plans.

Abstract: Systems, devices, kits, and methods are provided herein in the form of example embodiments that relate to calibration of medical devices. The medical devices can be sensors adapted to sense a biochemical attribute. The embodiments can be used to determine calibration information specific to an individual medical device. The embodiments can determine the calibration information by reference to one or more parameters obtained during manufacturing of the medical device. The embodiments can also determine the calibration information by reference to in vitro testing of the medical devices. The embodiments also apply to systems incorporating those medical devices in their use in the field. Also described are embodiments of modifications to surfaces of sensor substrates, such as through applied radiation and/or the creation of a well, to aid in the placement and/or sizing of a sensor element on the substrate.

Abstract: Surface-modified silica microparticles that are functionalized with stabilized phospholipid vesicles are described herein. These stabilized vesicles can be functionalized with either transmembrane receptors or membrane associated receptors and used for affinity pull-down assays or other chromatographic separation modalities to provide affinity capture/concentration of low abundance ligands in complex mixtures with minimal sample preparation. Further described are methods and apparatus for forming polymer frits in a fused silica capillary. The capillary containing a monomer solution is placed between one or more heat sources connected to each other via a jig and operatively coupled to a temperature controller. The polymer frits are synthesized via thermal polymerization of the monomer solution using the heat sources, which allows for placement of the polymer frits at a spatially-defined location in the capillary.

Abstract: A method according to this disclosure includes stacking a first glass sheet, a first interlayer, a film, a second interlayer, and a second glass sheet to provide a lamination stack, wherein the film has a first film edge that is a first distance from a first edge of the lamination stack to provide a first film cutback; deairing the lamination stack; and autoclaving the lamination stack to provide the laminated glazing, wherein the film shrinks during autoclaving wherein a seal formed during deairing is sufficient such that no air is introduced to the lamination stack during autoclaving and no air is left in the laminated glazing.

Abstract: A method for extracting path overhead (POH) data blocks from a data stream in a 64B/66B-block communication link, the method includes receiving at a sink node a data stream in a 64B/66B-block communication link, detecting within the data stream at a PCS sublayer a micro-packet starting with an /S/ control block, including K POH data blocks, and ending with a /T/ control block, extracting the micro-packet from the data stream, and extracting the POH data blocks from the micro-packet.

Abstract: Arthroplasty components include an articular surface and a bone-facing surface. The bone-facing surface includes a concave arrangement of planar surfaces which converge as they approach a middle portion of the articular surface. Instruments and implantation methods are also disclosed.

Abstract: Technologies for closed-looped testing of integrated circuit card payment terminals include loading a test profile onto an integrated circuit payment card. Authorization request and response messages are locally generated and translated to simulate acquirer processor processing and payment network processing. An outcome report indicative of the outcome of the test transaction is generated and transmitted to a remote certification server. Other embodiments are described and claimed.

Abstract: Disclosed herein are techniques associated with a Direct Memory Access (DMA) engine that can include a data generation module. The DMA engine can receive, from a processing entity, a particular type of write command with an indicator to write a data pattern to an address. Upon receipt of the particular type of write command, the DMA engine can generate, using a data generation module of the DMA engine, the data pattern to be written to the address. The processing entity can be Central Processing Unit (CPU) including a core configured to process serial commands. The DMA engine can be disposed on a same die as a processing entity or a network interface port.

Abstract: A subsurface diver transport vehicle includes a vehicle body and at least one propulsion device. The vehicle body incorporates a number of individual mission modules mechanically assembled together to define a substantially continuous hull and deck of the vehicle. The mission modules include at least one battery module adapted for supplying electrical current to electrical subsystems of the vehicle. The propulsion device is attached to the vehicle body and capable of propelling the vehicle through a body of water.

Abstract: Technologies for closed-looped testing of integrated circuit card payment terminals include loading a test profile onto an integrated circuit payment card. Authorization request and response messages are locally generated and translated to simulate acquirer processor processing and payment network processing. An outcome report indicative of the outcome of the test transaction is generated and transmitted to a remote certification server. Other embodiments are described and claimed.

Abstract: Provided are systems and methods for an address translation circuit for a memory controller. In various implementations, the address translation circuit includes an address translation table operable to include a subset of address translations for a processor memory. An address translation memory can include all address translations for the processor memory. The address translation circuit can be operable to receive an input address for a transaction to processor memory. The address translation circuit can determine an index for the address translation table by inputting the input address into a hash function. The address translation circuit can read a row from the address translation table using the index. The address translation circuit can determine whether an entry in the row includes an address translation for the input address. The address translation can generate and output a translated address using the address translation.

Abstract: A stemmed implant comprises a proximal body with a distal shaft extending from the proximal body. The proximal body exterior may be spherical, conical, cylindrical, or another surface of revolution. The distal shaft comprises multiple longitudinal ridges which may originate from the proximal body as separate columns, or which may merge together. The distal shaft and/or the ridges may become narrower as they extend away from the proximal body.

Abstract: A method for extracting POH data blocks and a MOS control block from a data stream in a 64B/66B-block communication link including receiving a data stream, finding a first combination of a MOS control block and K POH data blocks including CRC data in the data stream, extracting the MOS control block and the K POH data blocks from the data stream, searching in a window for a subsequent combination of a MOS control block and K POH data blocks and removing them if at least one of them are found, if neither the subsequent MOS control block nor the K POH data blocks are found within the predetermined window, extracting from the data stream K+1 64B/66B-blocks in the predetermined window.

Abstract: A method for rate adapting a constant bit rate (CBR) client signal into a signal stream in a telecom signal communication link includes at a source node encoding into a control block a control block header, and an ordered set block-designator, encoding into a plurality of path overhead data blocks a data block header and a count of data blocks to be encoded in a signal block, encoding into each of a plurality of signal blocks a data block header, the data blocks from the CBR signal equal to the count and pad blocks, assembling the blocks into a path signal frame, appending a set of idle character blocks following the end of the path signal frame to match a link bit rate of a first link segment, and transmitting the path signal frame and idle character blocks into the first link segment at the link bit rate.

Abstract: An automated wrapping system for wrapping a substrate with a material includes a support and a nest mounted to the support that is configured to position the material between an outer portion of the substrate and the nest. The automated wrapping system also includes a material folding assembly positioned adjacent to the nest configured for movement between a rest position and an actuated position, wherein the movement of the material folding system to the actuated position engages and folds the free end portion of the material over the edge of the substrate and onto a part of the inner portion of the substrate while retaining the material against the edge of the substrate. An actuator connected to the material folding assembly moves the material folding assembly between the rest position and the actuated position.

Abstract: Provided are systems and methods for an integrated circuit comprising a search engine, which a memory controller can use to manage a page table. In various implementations, the search engine can generate a series of read transactions to read the page table, which is stored in a memory. Each page table entry includes an address translation for processor memory. The memory controller may periodically change the address translations. The search engine can further determine whether data read from an entry in the page table corresponds to a search parameter. The search engine can further output a response, where the response is affirmative when the data read from the entry corresponds to the search parameters, and where the response is negative when no data read from any entry corresponds to the search parameter.

Abstract: Provided are systems and methods for an address translation circuit for a memory controller. The address translation circuit can include an address translation table. A first set of rows in the address translation table can be associated with all virtual machine identifiers supported by the memory controller. A second set of rows can be associated with only a particular virtual machine identifier. The address translation circuit can receive an input address for a transaction to processor memory. The address translation circuit can determine an index by inputting the input address into a hash function. The address translation circuit can read a row from the address translation table using the index. The address translation circuit can determine whether an entry in the row includes the address translation for the input address. The address translation circuit can generate and output a translated address using the address translation.

Abstract: A contiguous region in memory may be configured to store data so that a first portion of the data is addressable using a first indexing scheme and a second portion of the data is addressable using a second indexing scheme. The first portion of the data may include information which may be used by one entity and the second portion of the data may include different information which may be used by another entity.

Abstract: An analysis system may perform operations on an analyte that may be combined with multiple regents prior to being introduced into a flow cell. The instrument may include a volume into which the reagents to be combined with the analyte are aspirated one-by-one. The volume may be formed as a serpentine channel in a valve manifold associated with sippers for aspirating the reagents. The reagents may then be mixed by cycling a pump to move the reagents within the mixing volume or channel.

Abstract: A laminated glass product, according to the present disclosure, includes a first glass substrate, a second glass substrate, a polymer interlayer laminated between the first glass substrate and the second glass substrate, a functional film, such as a head-up display film, a printed film, and a switchable film, laminated between the first glass substrate and the second glass substrate, and a thin adhesive layer formed on the functional film between the functional film and one of the first and second glass substrates, for efficiently laminating such a functional film with improved lamination quality.