Abstract: Systems and methods are provided for supporting use of non-volatile memory (NVM) on a double data rate (DDR) memory channel for an information handling system so that non-volatile memory devices (e.g., such as Phase Change Memory “PCM” devices) may be employed for main memory usage. In one possible implementation, information handling system memory reads may be managed directly in hardware as memory semantics via use code, while memory writes may be separately handled, e.g., via an operating system (OS)/driver. In another possible implementation, both DRAM-based and NVM-based memory systems may be populated for an information handling system.

Abstract: In accordance with the present disclosure, a system and method for controller independent faulty memory replacement is described. The system includes a system memory component with a system memory component architecture. The system also includes a memory buffer coupled to the system memory component. The memory buffer may include at least one spare memory location corresponding to a faulty memory location of the system memory component. Additionally, the system memory component architecture may receive a read command directed to an address of the system memory component containing the faulty memory location and output, in response to the read command, data corresponding to the address from both the system memory component and the at least one spare memory component.

Abstract: A method of selectively enabling error checking in an information handling system, including receiving information indicating that data associated with a first memory portion in a system memory should be subject to error checking during transmission between the memory controller and the system memory and indicating that data associated with a second memory portion in the system memory should be free of error checking during transmission between the memory controller and the system memory, receiving a memory access request directed to one of the first and second memory portions, transmitting data between the memory controller and the system memory in response to the memory access request, and selectively performing an error checking technique on the transmitted data based on the information.

Abstract: An information handling system (IHS) includes a memory controller, a memory device, and firmware. A failing memory region and a spare memory region are included on the memory device. A memory buffer in the memory device is coupled to the failing memory region and the spare memory region. The memory buffer is operable to perform copy operations without instruction from the memory controller in order to copy data from the failing memory region to the spare memory region in response to firmware operations performed by the firmware. Firmware operations may include instructing the memory controller to produce additional refresh or calibration operation time periods, or providing an instruction to perform a data transfer operation to the spare memory region. The memory buffer is also operable to route requests from the memory controller to one of the failing memory region and the spare memory region during the copy operations.

Abstract: A supplemental power system for IHS power excursions includes a processor and a memory coupled to the processor. A power system is coupled to the processor and a plurality of power supply paths. A first power supply path is operable to supply power at a first voltage from the power system to the processor. A second power supply path is operable to store power from the power system at a second voltage that is greater than the first voltage, and the second power supply path is further operable to supply the power stored at the second voltage to the processor during power excursions by the processor. In some embodiments, the second power supply path may include a boost converter to increase power at the first voltage to the second voltage, or may receive power output at the second voltage from a supplemental power rail in the power system.

Abstract: A power management system includes a power system. A powered component is coupled to the power system. A power detect circuit is coupled to the power system. A power system controller is coupled to the power system, the powered component, and the power detect circuit. The power system controller is operable, for each of at least one workload run using the powered component, to program the power detect circuit with a first threshold for a first system operation setting and determine that the first threshold was not exceeded while the workload was running. The power system controller is then operable to program the power detect circuit with a second threshold for the first system operation setting, determine that the second threshold was exceeded while the workload was running and, in response, use the second threshold to allocate power from the power system.

Abstract: A dynamic power budget allocation system includes a plurality of powered subsystems. A power system controller is coupled to the plurality of powered subsystems. The power system controller is operable, for each of a plurality of time intervals, to retrieve power usage data from each of the plurality of subsystems during a current time interval. The power system controller is then operable to project power requirements for the plurality of subsystems for a subsequent time interval using the power usage data. The power system controller is then operable to determine at least one power setting for at least one of the plurality of subsystems using the power requirements, and program the at least one of the plurality of subsystems with the at least one power setting. Each powered subsystem may include a voltage regulator that provides the power usage data and is programmed with the at least one power setting.

Abstract: A power supply system for an information handling system is disclosed. The power supply system includes power supply units electrically coupled via an output line. The power supply units are configured to supply an output voltage to the output line. Each power supply unit receives a feedback signal indicative of a voltage of the output line and a programmed voltage signal indicative of a supply voltage required for the output line. A standby power supply unit is configured to transition between a standby mode and an active mode based, at least in part, on the feedback signal and the programmed voltage signal. Power supply units are configured to transition to a load sharing mode where the power supply units cooperatively supply an output voltage to the output line. The transitioning is based, at least in part, on the feedback signal and the programmed voltage signal.

Abstract: A method of selectively enabling error checking in an information handling system, including receiving information indicating that data associated with a first memory portion in a system memory should be subject to error checking during transmission between the memory controller and the system memory and indicating that data associated with a second memory portion in the system memory should be free of error checking during transmission between the memory controller and the system memory, receiving a memory access request directed to one of the first and second memory portions, transmitting data between the memory controller and the system memory in response to the memory access request, and selectively performing an error checking technique on the transmitted data based on the information.

Abstract: An apparatus including a first connector configured to fit into a first socket in a processing system, the first connector and first socket conforming to a first standard, a second socket configured to accept a memory module therein, the second socket and the memory module conforming to a second standard, a memory buffer module communicatively coupled to the first connector and the second socket, the memory buffer module configured to receive signals associated with the first standard from the first connector and output signals associated with the second standard to the second socket, and a virtualization module communicatively coupled to the memory buffer module, the first connector, and the second socket, the virtualization module configured to receive first initialization data associated with the second standard from the second socket and output second initialization data associated with the first standard to the processing system.

Abstract: In one aspect, a method for improving reliability and availability of an information handling system is disclosed. Operational data associated with an operating margin may be captured. A threshold specified by a pre-defined profile may be identified. The pre-defined profile may be useable in adjusting the operating margin. The captured operational data may be compared to the pre-defined threshold. A parameter specified by the pre-defined profile may be identified. The operation of a component of the information handling system may be modified based, at least in part, on the identified parameter specified by the pre-defined profile. The modification may result in adjusting the operating margin.

Abstract: Systems and methods for safe handling of information handling resources are provided. In some embodiments, a method is provided. The method may include detecting occurrence of a power down sequence and in response to detecting of the power down sequence, controlling operation of a cooling fan coupled to information handling resources based at least on a first criteria of a predetermined policy. The method may include receiving a signal from a sensor, the signal indicating a thermal property of a particular information handling resource coupled to the sensor. The method may include determining if the thermal property satisfies a second criteria of the predetermined policy, the second criteria comprising a safe temperature range for handling the particular information handling resource. If the thermal property meets the second criteria, the method may provide an alert via an indicator to a user indicating the particular information handling resource is safe for handling.

Abstract: A power management control system for an information handling system is disclosed. The power management control system includes a power management interface bus interfacing a plurality of devices, where one or more of the devices is each associated with a time clock. The power management control system further includes a management agent interfacing the power management interface bus. The management agent is configured to: receive a system time; synchronize the one or more time clocks based, at least in part, on the system time; and maintain synchronization of the one or more time clocks, at least in part, via a set of telemetric primitives.

Abstract: The present disclosure involves an apparatus. The apparatus includes a decoder that receives an input command signal as its input and generates a first output command signal as its output. The apparatus includes a register component that receives the input command signal as its input and generates a second output command signal as its output. The apparatus further includes a multiplexer that receives a control signal as its control input and receives both the first output command signal and the second output command signal as its data input, the multiplexer being operable to route one of the first and second output command signals to its output in response to the control signal.

Abstract: An information handling system (IHS) includes a memory controller, a memory device, and firmware. A failing memory region and a spare memory region are included on the memory device. A memory buffer in the memory device is coupled to the failing memory region and the spare memory region. The memory buffer is operable to perform copy operations without instruction from the memory controller in order to copy data from the failing memory region to the spare memory region in response to firmware operations performed by the firmware. Firmware operations may include instructing the memory controller to produce additional refresh or calibration operation time periods, or providing an instruction to perform a data transfer operation to the spare memory region. The memory buffer is also operable to route requests from the memory controller to one of the failing memory region and the spare memory region during the copy operations.

Abstract: Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. A method for reducing power consumption in memory may include tracking, by an operating system executing on a processor, one or more logical units of a memory system that are in use. The method may also include setting, by the operating system, a variable indicating a portion of the memory system in use based on the logical units of the memory system in use. The method may additionally include refreshing one or more of the one or more logical units of the memory system based on the variable.

Abstract: Systems and methods are disclosed for providing a signal indicative of one or more types of individual measurable device characteristic/s that are unique to a given electronic device by providing a signal indicative of the measurable and unique device characteristic/s in a passive manner from the electronic device. The signal indicative of one or more types of individual measurable device characteristic/s may be so provided without requiring operational power to be applied to any active electronic circuitry of the device, and without requiring any power to be generated by the device.

Abstract: A power management control system for an information handling system is disclosed. The power management control system includes a power management interface bus interfacing a plurality of devices, where one or more of the devices is each associated with a time clock. The power management control system further includes a management agent interfacing the power management interface bus. The management agent is configured to: receive a system time; synchronize the one or more time clocks based, at least in part, on the system time; and maintain synchronization of the one or more time clocks, at least in part, via a set of telemetric primitives.

Abstract: A bee feeder assembly is provided, including a receptacle, a cover member and a ladder arrangement. The ladder arrangement includes at least one ladder member comprising a porous member depending downwardly from the cover member. Methods of assembly and use are described.

Abstract: Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. A method for reducing power consumption in memory may include tracking, by an operating system executing on a processor, one or more logical units of a memory system that are in use. The method may also include setting, by the operating system, a variable indicating a portion of the memory system in use based on the logical units of the memory system in use. The method may additionally include refreshing one or more of the one or more logical units of the memory system based on the variable.