Patents by Inventor Stuart Allen

Stuart Allen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods for automatic detection and configuration of voltage regulator phases in a multi-rail voltage regulator
    Patent number: 9612638
    Abstract: A method may include, in an information handling system comprising a power system having a plurality of voltage regulator phases, during a configuration mode of the power system, determining connectivity between the plurality of voltage regulator phases and a primary power rail and connectivity between the plurality of voltage regulator phases and a secondary power rail based on population of output inductors in one or more of a plurality of first phase output inductor footprint locations or one or more of a plurality of second phase output inductor footprint locations, wherein each of the plurality of phase output inductor footprint locations is respectively coupled to an first output of a respective voltage regulator phase of the plurality of voltage regulator phases and is coupled to a respective power rail of the information handling system.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: April 4, 2017
    Assignee: Dell Products L.P.
    Inventors: Stuart Allen Berke, Abey K. Mathew
  • System and Method of Selective Encoding for Enhanced Serializer/Deserializer Throughput
    Publication number: 20170093521
    Abstract: A serial communication link including first and second components. The first component includes a first management module and a first encoder that provides A-bit/B-bit encoded data to a first channel, where A<B. The second component includes a second management module and a first decoder/bit-error-rate (BER) module that receives the A-bit/B-bit encoded data from the first channel, determines a BER associated with the A-bit/B-bit encoded data, and provides an indication to the second management module when the BER is higher than a threshold BER level. The second management module communicates the indication to the first management module, and the first management module directs the first encoder to provide C-bit/D-bit encoded data to the first channel in response to receiving the indication, where C<D, C<A, and D<B.
    Type: Application
    Filed: September 28, 2015
    Publication date: March 30, 2017
    Inventors: Minchuan Wang, Stuart Allen Berke, Bhyrav M. Mutnury
  • System and Method to Blacklist Equalization Coefficients in a High-Speed Serial Interface
    Publication number: 20170091137
    Abstract: A serial interface comprises a receiver including a first input compensation module with a first setting that selects a first value from among a plurality of first values for a first input characteristic of the receiver, a memory to store a first blacklist value from among the first values, and a control module to select each of the first values, except for the first blacklist value, to evaluate an indication of a performance level of the receiver for each of the selected first values, and to select a particular first value based upon the indications of the performance level of the receiver.
    Type: Application
    Filed: September 28, 2015
    Publication date: March 30, 2017
    Inventors: Stuart Allen Berke, Bhyrav M. Mutnury
  • Power Aware Receiver/Transmitter Adaptation for High Speed Serial Interfaces
    Publication number: 20170085400
    Abstract: A receiver includes first and second equalization modules adapted to provide first and second compensations to a data signal, and a control module including a list that identifies the first equalization module as being less efficient than the second. The control module provides first and second compensation levels of the first and second compensations, such that the first and second compensations operate on the data signal to meet a bit error rate (BER) target, lowers the first compensation to reduce the power consumption of the receiver based on the list, and determines whether, in response to an increase in the level of the second compensation the BER target is met.
    Type: Application
    Filed: November 30, 2016
    Publication date: March 23, 2017
    Inventors: Stuart Allen Berke, Bhyrav M. Mutnury, Minchuan Wang
  • SYSTEMS AND METHODS FOR VIRTUAL CURRENT SHARING BETWEEN A POWER SUPPLY UNIT AND A BATTERY BACK-UP UNIT
    Publication number: 20170068294
    Abstract: In accordance with embodiments of the present disclosure, a battery back-up unit for supplying electrical energy to an information handling resource via a power bus in response to a power event affecting an ability of a power supply unit to deliver electrical energy to the information handling resource via the power bus may be configured to, in response to the power event and prior to the power supply unit ceasing to deliver electrical energy to the power bus monitor a current share bus having a current share signal driven at least in part by the power supply unit, the current share signal indicative of a first current driven by the power supply unit to the power bus, drive a second current to the power bus in accordance with the current share signal, and refrain from driving the current share bus.
    Type: Application
    Filed: September 3, 2015
    Publication date: March 9, 2017
    Inventors: Lei Wang, John Erven Jenne, Stuart Allen Berke, Sanjiv Catibog Sinha
  • SYSTEMS AND METHODS FOR HIDDEN BATTERY CELL CHARGING AND CONDITIONING
    Publication number: 20170063108
    Abstract: In accordance with embodiments of the present disclosure, an information handling system may include at least one information handling resource and a battery for supplying electrical energy to the at least one information handling resource. The battery may include a plurality of series-coupled cells and a plurality of switching devices arranged with respect to the plurality of series-coupled cells, the plurality of switching devices configured to be selectively and independently activated and deactivated in order to simultaneously enable one or more of the plurality of series-coupled cells to generate a portion of an output voltage delivered to the at least one information handling resource and bypass one or more of the plurality of series-coupled cells.
    Type: Application
    Filed: August 28, 2015
    Publication date: March 2, 2017
    Inventors: Lei Wang, Stuart Allen Berke
  • INFORMATION HANDLING SYSTEM WITH PERSISTENT MEMORY AND ALTERNATE PERSISTENT MEMORY
    Publication number: 20170060697
    Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a primary persistent memory comprising a volatile memory for storing data and a non-volatile memory for receiving data transferred from the volatile memory in response to a power loss of the information handling system. The information handling system may also include an alternate persistent memory instructions embodied in non-transitory computer readable media, the instructions for causing a processor communicatively coupled to the primary persistent memory and the alternate persistent memory to, responsive to a vulnerability of a persistence of the primary persistent memory, transfer application data from the primary persistent memory to the alternate persistent memory.
    Type: Application
    Filed: August 24, 2015
    Publication date: March 2, 2017
    Inventors: Stuart Allen Berke, John Erven Jenne, Shane Michael Chiasson
  • SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION OF MEMORY
    Publication number: 20170052727
    Abstract: Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. In accordance with one embodiment of the present disclosure, a method for improving performance and reducing power consumption in memory may include tracking whether individual units of a memory system are active or inactive. The method may also include placing inactive individual units of the memory system in a self-refresh mode, such that the inactive individual units self-refresh their contents. The method may further include placing active individual units of the memory system in a command-based refresh mode, such that the active individual units are refreshed in response to a received command to refresh their contents.
    Type: Application
    Filed: August 12, 2016
    Publication date: February 23, 2017
    Inventors: William Sauber, Stuart Allen Berke
  • SYSTEMS AND METHODS TO OPTIMIZE BOOT FOR INFORMATION HANDLING SYSTEM COMPRISING PERSISTENT MEMORY
    Publication number: 20170052794
    Abstract: A basic input/output system may be configured to, during boot of an information handling system in a pre-operating system environment of the information handling system, calculate an amount of energy required to perform a persistent memory save operation in a persistent memory of the information handling system in order to transfer data from a volatile memory of the persistent memory communicatively coupled to the processor to a non-volatile memory of the persistent memory communicatively coupled to the volatile memory, cause charging of an energy storage device for providing electrical energy to perform persistent memory save operations at least until a charging level of the energy storage device satisfies the amount of energy, and boot to an operating system of the information handling system responsive to the charging level of the energy storage device satisfying the amount of energy.
    Type: Application
    Filed: August 20, 2015
    Publication date: February 23, 2017
    Inventors: Stuart Allen Berke, Shane Michael Chiasson
  • SYSTEMS AND METHODS FOR REAL-TIME CACHE FLUSH MEASUREMENTS IN AN INFORMATION HANDLING SYSTEM
    Publication number: 20170052791
    Abstract: In accordance with embodiments of the present disclosure, a method may include, during boot of an information handling system, determining a first amount of energy required by the information handling system to flush a cache integral to the information handling system to memory integral to the information handling system in response to a power loss of one or more power supplies for supplying electrical energy to the information handling system, determining whether a second amount of energy available for hold-up of one or more power supplies in response to the power loss exceeds the first amount of energy, and responsive to determining whether the second amount of energy exceeds the first amount of energy, configuring the cache.
    Type: Application
    Filed: August 21, 2015
    Publication date: February 23, 2017
    Inventors: John Erven Jenne, Stuart Allen Berke, Dit Charoen
  • Dynamic power budget allocation
    Patent number: 9568966
    Abstract: A dynamic power budget allocation system includes a plurality of powered subsystems. A power system controller is coupled to the plurality of powered subsystems. The power system controller is operable, for each of a plurality of time intervals, to retrieve power usage data from each of the plurality of subsystems during a current time interval. The power system controller is then operable to project power requirements for the plurality of subsystems for a subsequent time interval using the power usage data. The power system controller is then operable to determine at least one power setting for at least one of the plurality of subsystems using the power requirements, and program the at least one of the plurality of subsystems with the at least one power setting. Each powered subsystem may include a voltage regulator that provides the power usage data and is programmed with the at least one power setting.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: February 14, 2017
    Assignee: Dell Products L.P.
    Inventors: Stuart Allen Berke, George G. Richards, III
  • Systems and methods for data alignment in a memory system
    Patent number: 9563384
    Abstract: A method may include link training a plurality of back-side lanes coupling a plurality of memory chips of a memory module to a plurality of data buffers of the memory module. The method may also include link training a plurality of front-side lanes coupling the plurality of data buffers to a memory controller. The method may further include determining after link training of the back-side and front-side lanes whether signal integrity of data communicated over the front-side lanes exceeds one or more thresholds. The method may additionally include responsive to determining that the signal integrity of data communicated over one or more of the front-side lanes fails to exceed the one or more thresholds, modifying timing of data communicated over one or more of the back-side and front-side lanes in order to improve signal integrity of the one or more of the front-side lanes failing to exceed the thresholds.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: February 7, 2017
    Assignee: Dell Products L.P.
    Inventors: Stuart Allen Berke, Bhyrav M. Mutnury, Vadhiraj Sankaranarayanan
  • METHODS OF POWER SUPPLY UNIT ROTATING IN AN INFORMATION HANDLING SYSTEM
    Publication number: 20170017293
    Abstract: A method of power supply unit rotating in an information handling system (IHS) may include a control unit dividing a power loading of an IHS into N sections, where N corresponds to a number of power supply units coupled to the IHS. The control unit may configure a first power supply unit to an active state and configure one or more remaining power supply units to a suspended state during a first time period. The control unit may configure the first power supply unit to the suspended state and configure a second power supply unit to the active state in response to a second time period being reached. The control unit may rotate the active state among the power supply units in response to sequential time periods being reached. In an embodiment the control unit may rotate the active state sequentially between each of the subsequent power supplies.
    Type: Application
    Filed: December 31, 2014
    Publication date: January 19, 2017
    Applicant: DELL PRODUCTS, L.P.
    Inventors: Mark A. Muccini, Mehran Mirjafari, William Draper, Ashish Razdan, Wei Wang, John Evren Jenne, Stuart Allen Berke
  • Power aware receiver/transmitter adaptation for high speed serial interfaces
    Patent number: 9531569
    Abstract: A receiver includes first and second equalization modules adapted to provide first and second compensations to a data signal, and a control module including a list that identifies the first equalization module as being less efficient than the second. The control module provides first and second compensation levels of the first and second compensations, such that the first and second compensations operate on the data signal to meet a bit error rate (BER) target, lowers the first compensation to reduce the power consumption of the receiver based on the list, and determines whether, in response to an increase in the level of the second compensation the BER target is met.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: December 27, 2016
    Assignee: Dell Products, LP
    Inventors: Stuart Allen Berke, Bhyrav M. Mutnury, Minchuan Wang
  • SYSTEMS AND METHODS FOR DATA ALIGNMENT IN A MEMORY SYSTEM
    Publication number: 20160321014
    Abstract: A method may include link training a plurality of back-side lanes coupling a plurality of memory chips of a memory module to a plurality of data buffers of the memory module. The method may also include link training a plurality of front-side lanes coupling the plurality of data buffers to a memory controller. The method may further include determining after link training of the back-side and front-side lanes whether signal integrity of data communicated over the front-side lanes exceeds one or more thresholds. The method may additionally include responsive to determining that the signal integrity of data communicated over one or more of the front-side lanes fails to exceed the one or more thresholds, modifying timing of data communicated over one or more of the back-side and front-side lanes in order to improve signal integrity of the one or more of the front-side lanes failing to exceed the thresholds.
    Type: Application
    Filed: July 11, 2016
    Publication date: November 3, 2016
    Applicant: Dell Products L.P.
    Inventors: Stuart Allen BERKE, Bhyrav M. MUTNURY, Vadhiraj SANKARANARAYANAN
  • Systems and methods for data alignment in a memory system
    Patent number: 9417802
    Abstract: A method may include link training a plurality of back-side lanes coupling a plurality of memory chips of a memory module to a plurality of data buffers of the memory module. The method may also include link training a plurality of front-side lanes coupling the plurality of data buffers to a memory controller. The method may further include determining after link training of the back-side and front-side lanes whether signal integrity of data communicated over the front-side lanes exceeds one or more thresholds. The method may additionally include responsive to determining that the signal integrity of data communicated over one or more of the front-side lanes fails to exceed the one or more thresholds, modifying timing of data communicated over one or more of the back-side and front-side lanes in order to improve signal integrity of the one or more of the front-side lanes failing to exceed the thresholds.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: August 16, 2016
    Assignee: Dell Products L.P.
    Inventors: Stuart Allen Berke, Bhyrav M. Mutnury, Vadhiraj Sankaranarayanan
  • System Aware Transmitter Adaptation for High Speed Serial Interfaces
    Publication number: 20160211992
    Abstract: A high-speed serial interface includes a transmitter having an output module with settings that select an output impedances of the output module and a tuning value for the output impedance, and a receiver having a plurality of compensation modules each to provide a selectable level of equalization to a data bitstream from the transmitter, and a control module that directs the transmitter to successively select each of the tuning values, that directs the compensation modules, for each tuning value, to successively select each of the levels of equalization, that evaluates an indication of a performance level of the receiver for each of the successively selected levels of equalization and for each of the tuning values, and that selects a particular tuning value based upon the indications of the performance level of the receiver.
    Type: Application
    Filed: March 29, 2016
    Publication date: July 21, 2016
    Inventors: Stuart Allen Berke, Bhyrav M. Mutnury
  • Power management system
    Patent number: 9395790
    Abstract: A power management system includes a power system. A powered component is coupled to the power system. A power detect circuit is coupled to the power system. A power system controller is coupled to the power system, the powered component, and the power detect circuit. The power system controller is operable, for each of at least one workload run using the powered component, to program the power detect circuit with a first threshold for a first system operation setting and determine that the first threshold was not exceeded while the workload was running. The power system controller is then operable to program the power detect circuit with a second threshold for the first system operation setting, determine that the second threshold was exceeded while the workload was running and, in response, use the second threshold to allocate power from the power system.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: July 19, 2016
    Assignee: Dell Products L.P.
    Inventors: Stuart Allen Berke, George G. Richards, III
  • Adjustable heat sink supporting multiple platforms and system configurations
    Patent number: 9377828
    Abstract: An adjustable heat sink which allows factory, service, or customers to adjust the width of the heat sink to take advantage of some or all available unpopulated DIMM space to optimize cooling and performance. Such an adjustable heat sink addresses many of the limitations of other heat sinks and is advantageous for reducing part numbers within a platform and across platforms. Such an adjustable heat sink also simplifies field upgrades when either adding or removing populated DIMMs to an information handling system thus enhancing performance without a need to change CPU Heat sinks.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: June 28, 2016
    Assignee: Dell Products L.P.
    Inventors: Eric M. Tunks, Stuart Allen Berke
  • System and Method for Providing Kernel Intrusion Prevention and Notification
    Publication number: 20160179704
    Abstract: A memory protection module includes comparison logic that has a write-once window CSR that stores a memory address range, and window protection logic. The comparison logic receives a memory write transaction, determines a memory address of the memory write transaction, and provides an indication as to whether or not the memory address is included in the memory address range. The window protection logic receives the memory transaction, receives the indication from the comparison logic, allows the memory write transaction to proceed in response to the indication indicating that the memory address is not included in the memory address range, and drops the memory write transaction in response to the indication indicating that the memory address is included in the memory address range.
    Type: Application
    Filed: December 19, 2014
    Publication date: June 23, 2016
    Inventors: Stuart Allen Berke, Mi Wang, Vivek Dharmadhikari