Abstract: A semiconductor structure and a method of making the same includes a first recessed region in a semiconductor structure, the first recessed region defining a first opening with a first positive tapering profile, as at least part of the first positive tapering profile, widening the first opening in a direction towards a top source/drain region of the semiconductor structure at a first tapering angle, and a top source/drain contact within the first opening, the top source/drain contact surrounding a surface of the top source/drain region. The semiconductor structure further includes a protective liner located at an interface between a bottom portion of the top source/drain region, a top spacer adjacent to the top source/drain region and a dielectric material between two consecutive top source/drain regions, the protective liner protects the top source/drain regions during contact patterning.

Abstract: A semiconductor structure comprises two or more vertical fins, a bottom epitaxial layer surrounding a bottom portion of a given one of the two or more vertical fins, a top epitaxial layer surrounding a top portion of the given one of the two or more vertical fins, a shared epitaxial layer surrounding a middle portion of the given one of the two or more vertical fins, and a connecting layer contacting the bottom epitaxial layer and the top epitaxial layer, the connecting layer being disposed to a lateral side of the two or more vertical fins.

Abstract: A method of forming stacked fin field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first semiconductor layer on a surface of the substrate, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, a separation layer on the third semiconductor layer, a fourth semiconductor layer on the separation layer, a fifth semiconductor layer on the fourth semiconductor layer, and a sixth semiconductor layer on the fifth semiconductor layer. The method further includes forming a plurality of channels through the layer stack to the surface of the substrate, and removing portions of the second semiconductor layer and fifth semiconductor layer to form lateral grooves.

Abstract: A method is presented for forming a self-aligned middle-of-the-line (MOL) contact. The method includes forming a fin structure over a substrate, depositing and etching a first set of dielectric layers over the fin structure, etching the fin structure to form a sacrificial fin and a plurality of active fins, depositing a work function metal layer over the plurality of active fins, depositing an inter-layer dielectric (ILD) and a second set of dielectric layers. The method further includes etching the second set of dielectric layers and the ILD to form a first via portion and to expose a top surface of the sacrificial fin, removing the sacrificial fin to form a second via portion, and filling the first and second via portions with a conductive material to form the MOL contact in the first via portion and a contact landing in the second via portion.

Abstract: Chromatin 3D structure modulating agents in the context of the present invention are intended to interfere or manipulate the function of loop anchor motifs, such as CTCF motifs. In certain example embodiments, the present invention may block formation of an loop anchor or chromatin domain or induce formation of a loop anchor or chromatin domain at a targeted genomic location. For instance, a loop anchor motif can be altered, such as by mutating (including inverting) a binding motif so as to remove such a motif, or by adding new binding motifs in new locations within a loop domain, so as to reduce the size of an existing loop, so as to modify the size of an existing loop, or combinations thereof. Alternatively, the chromatin 3D structure modulating agent may bind a target region and mask a loop anchor motif, thereby preventing a loop anchor or chromatin domain from forming. The chromatin 3D structure modulating agent may bind a target region and cause a loop anchor of chromatin domain to form.

Abstract: A display device includes a viewing angle control panel and a backlight module. The backlight module is arranged below the viewing angle control panel, and includes a light source and an optical adjustment layer. The optical adjustment layer includes a first surface, a second surface and a plurality of openings. The second surface is arranged in opposite to the first surface and in proximity to the light source. The plurality of openings pass through the optical adjustment layer.

Abstract: Devices and techniques are generally described for scheduling optimization. In some examples, at least one processor may receive labor order data describing a plurality of work shifts and a respective number of candidates requested for each work shift of the plurality of work shifts. In various examples, an optimized set of schedules may be determined by solving an optimization problem based at least in part on the labor order data and a candidate preference signal representing a predicted popularity of proposed schedules for candidate workers. The optimized set of schedules may selected based on the respective number of candidates requested for each work shift and further based on historical candidate preferences. In at least some examples, first code may be generated that is effective to cause the optimized set of schedules to be displayed by a first computing device.

Abstract: A method for fabricating a semiconductor device includes forming top source/drain contact material on top source/drain material disposed on one or more fins of a base structure, and subtractively patterning the top source/drain contact material to form at least one top source/drain contact. The at least one top source/drain contact has a positive tapered geometry. The method further includes cutting exposed end portions of the top source/drain material to form at least one top source/drain region underneath the at least one top source/drain contact.

Abstract: A method of forming stacked fin field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first semiconductor layer on a surface of the substrate, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, a separation layer on the third semiconductor layer, a fourth semiconductor layer on the separation layer, a fifth semiconductor layer on the fourth semiconductor layer, and a sixth semiconductor layer on the fifth semiconductor layer. The method further includes forming a plurality of channels through the layer stack to the surface of the substrate, and removing portions of the second semiconductor layer and fifth semiconductor layer to form lateral grooves.

Abstract: An electronic device includes a display panel and a viewing angle control unit disposed opposite to the display panel. The viewing angle control unit includes a first substrate; a second substrate disposed opposite to the first substrate; a plurality of protrusions disposed between the first substrate and the second substrate; and a plurality of shielding units disposed between the first substrate and the second substrate and disposed corresponding to the plurality of protrusions. One of the shielding units forms a first projection on the first substrate, one of the protrusions forms a second projection on the first substrate, and the second projection falls within the first projection.

Abstract: Chromatin 3D structure modulating agents in the context of the present invention are intended to interfere or manipulate the function of loop anchor motifs, such as CTCF motifs. In certain example embodiments, the present invention may block formation of an loop anchor or chromatin domain or induce formation of a loop anchor or chromatin domain at a targeted genomic location. For instance, a loop anchor motif can be altered, such as by mutating (including inverting) a binding motif so as to remove such a motif, or by adding new binding motifs in new locations within a loop domain, so as to reduce the size of an existing loop, so as to modify the size of an existing loop, or combinations thereof. Alternatively, the chromatin 3D structure modulating agent may bind a target region and mask a loop anchor motif, thereby preventing a loop anchor or chromatin domain from forming. The chromatin 3D structure modulating agent may bind a target region and cause a loop anchor of chromatin domain to form.

Abstract: MOL non-SAC structures and techniques for formation thereof are provided. In one aspect, a method of forming a semiconductor device includes: patterning fins in a substrate; forming gates over the fins and source/drains offset by gate spacers; lining upper sidewalls of the gates with a first dielectric liner; depositing a source/drain metal; lining upper sidewalls of the source/drain metal with a second dielectric liner; depositing a dielectric over the gates and source/drains; forming a first via in the dielectric which exposes the second dielectric liner over a select source/drain; removing the second dielectric liner from the select source/drain; forming a second via in the dielectric which exposes the first dielectric liner over a select gate; removing the first dielectric liner from the select gate; forming a source/drain contact in the first via; and forming a gate contact in the second via. A semiconductor device is also provided.

Abstract: Embodiments of the invention are directed to an interconnect stack including a first dielectric layer, a first trench formed in the first dielectric layer, and a first liner deposited in the first trench, wherein the first liner defines a second trench. A first conductive material is in the second trench and deposited over the first dielectric layer and the first conductive material. A third trench extends through the second dielectric layer and is over the first conductive material. A bottom surface of the third trench includes at least a portion of the top surface of the first conductive material. A second liner is in the third trench, on sidewalls of the third trench, and also on the portion of the top surface of the first conductive material. The second liner functions as a cap region configured to counter electro-migration or surface migration of the first conductive material.

Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor structure in a first device region on a substrate, and forming a second vertical transistor structure in a second device region on the substrate. The first vertical transistor structure includes a first plurality of fins, and the second vertical transistor structure includes a second plurality of fins. A plurality of first source/drain regions are grown from upper portions of the first plurality of fins, and a contact liner layer is formed on the first source/drain regions. The method further includes forming a plurality of first silicide portions from the contact liner layer on the first source/drain regions, and forming a plurality of second silicide portions on a plurality of second source/drain regions extending from upper portions of the second plurality of fins. The second silicide portions have a different composition than the first silicide portions.

Abstract: Semiconductor device layout designs for Vt tuning are provided. In one aspect, a semiconductor device is provided. The semiconductor device includes: at least one first metal line in contact with a source or drain of an FET; at least one second metal line in contact with a gate of the FET, wherein the first metal line crosses the second metal line; and an oxygen diffusion blocking layer on top of the at least one first metal line in an overlap area of the at least one first metal line and the at least one second metal line. A method of forming a semiconductor device is also provided.

Abstract: One or more computing devices, systems, and/or methods for cross-domain action prediction are provided. Action sequence embeddings are generated based upon a textual embedding and a graph embedding utilizing past user action sequences corresponding to sequences of past actions performed by users across a plurality of domains. An autoencoder is trained to utilize the action sequence embeddings to project the action sequence embeddings to obtain intent space vectors. A service switch classifier is trained using the intent space vectors. In response to the service switch classifier predicting that a current user will switch from a current domain to a next domain, the current user is provided with a recommendation of an action corresponding to the next domain.

Abstract: A method of forming stacked fin field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first semiconductor layer on a surface of the substrate, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, a separation layer on the third semiconductor layer, a fourth semiconductor layer on the separation layer, a fifth semiconductor layer on the fourth semiconductor layer, and a sixth semiconductor layer on the fifth semiconductor layer. The method further includes forming a plurality of channels through the layer stack to the surface of the substrate, and removing portions of the second semiconductor layer and fifth semiconductor layer to form lateral grooves.

Abstract: Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes forming a first layer of the multi-layered IC structure, wherein the first layer includes a trench having a liner and a conductive interconnect formed in the trench. The liner is formed such that it is not on a portion of a sidewall of the conductive interconnect. A multi-segmented cap is formed having a first cap segment and a second cap segment. The first cap segment is on a top surface of the conductive interconnect, and a first portion of the second cap segment is on the portion of the sidewall of the conductive interconnect. The second cap segment is on a top surface of the first cap segment.

Abstract: Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes forming a first layer of the multi-layered IC structure, wherein the first layer includes a trench having a liner and a conductive interconnect formed in the trench. The liner is formed such that it is not on a portion of a sidewall of the conductive interconnect. A multi-segmented cap is formed having a first cap segment and a second cap segment. The first cap segment is on a top surface of the conductive interconnect, and a first portion of the second cap segment is on the portion of the sidewall of the conductive interconnect. The second cap segment is on a top surface of the first cap segment.

Abstract: A semiconductor device includes a first interconnect structure formed in an MX level of the semiconductor device, the MX level includes a third interlevel dielectric layer located above a second capping layer, a first trench within the third interlevel dielectric layer extending through the second capping layer to expose a top surface of a contact structure located below the second capping layer, the contact structure is located within a second interlevel dielectric layer, a second metal liner conformally deposited within the first trench, and a first seed layer conformally deposited above the second metal liner, the first seed layer includes a metal manganese film. A first thermal annealing process is conducted on the semiconductor device to form a first barrier liner underneath the second metal liner to prevent diffusion of conductive metals.