Abstract: Methods are presented for forming multi-threshold field effect transistors. The methods generally include depositing and patterning an organic planarizing layer to protect underlying structures formed in a selected one of the nFET region and the pFET region of a semiconductor wafer. In the other one of the nFET region and the pFET region, structures are processed to form an undercut in the organic planarizing layer. The organic planarizing layer is subjected to a reflow process to fill the undercut. The methods are effective to protect a boundary between the nFET region and the pFET region.

Abstract: This disclosure describes one or more implementations of a depth prediction system that generates accurate depth images from single input digital images. In one or more implementations, the depth prediction system enforces different sets of loss functions across mix-data sources to generate a multi-branch architecture depth prediction model. For instance, in one or more implementations, the depth prediction model utilizes different data sources having different granularities of ground truth depth data to robustly train a depth prediction model. Further, given the different ground truth depth data granularities from the different data sources, the depth prediction model enforces different combinations of loss functions including an image-level normalized regression loss function and/or a pair-wise normal loss among other loss functions.

Abstract: The present disclosure relates to systems, non-transitory computer-readable media, and methods for utilizing machine learning models to generate refined depth maps of digital images utilizing digital segmentation masks. In particular, in one or more embodiments, the disclosed systems generate a depth map for a digital image utilizing a depth estimation machine learning model, determine a digital segmentation mask for the digital image, and generate a refined depth map from the depth map and the digital segmentation mask utilizing a depth refinement machine learning model. In some embodiments, the disclosed systems generate first and second intermediate depth maps using the digital segmentation mask and an inverse digital segmentation mask and merger the first and second intermediate depth maps to generate the refined depth map.

Abstract: A high aspect ratio contact structure formed within a dielectric material includes a top portion and a bottom portion. The top portion of the contact structure includes a tapering profile towards the bottom portion. A first metal stack surrounded by an inner spacer is located within the top portion of the contact structure and a second metal stack is located within the bottom portion of the contact structure. A width of the bottom portion of the contact structure is greater than a minimum width of the top portion of the contact structure.

Abstract: An approach forming semiconductor structure composed of one or more stacked semiconductor devices that include at least a top semiconductor device, a bottom semiconductor device under the top semiconductor, and contacts to each of the semiconductor devices. The approach provides a stacked semiconductor structure where the bottom semiconductor device is wider than the top semiconductor device. The approach also provides the stacked semiconductor structure where the width of the top semiconductor device is the same as the width of the bottom semiconductor device. The approach includes forming a contact to a side of the bottom semiconductor device when the width of the top semiconductor device is the same as the bottom semiconductor device. The approach includes forming a contact to epitaxy grown on a portion of the top and a side of the bottom semiconductor device when the bottom semiconductor device is larger than the top semiconductor device.

Abstract: A semiconductor device including a first nanodevice is located on a substrate, where the first nanodevice includes at least one channel. A first source/drain connected to the first nanodevice. A second nanodevice located on the substrate, where the second nanodevice includes at least one channel and a second source/drain connected to the second nanodevice. A first contact located above the first source/drain. A second contact located above the second source/drain. A contact cap located on top of the first contact and the second contact, where the contact cap has a first leg that extends downwards between the first contact and the second contact. The first leg of the contact cap is in contact with a first sidewall of the first contact, and a first sidewall of the second contact.

Abstract: Embodiments of present invention provide a semiconductor device. The semiconductor structure includes a plurality of nanosheet (NS) channel layers having a plurality of source/drain (S/D) regions on sidewalls thereof; and a continuous contact via being in direct contact with the plurality of S/D regions, wherein the continuous contact via has a substantially same horizontal distance to each of the plurality of NS channel layers. A method of manufacturing the same is also provided.

Abstract: A semiconductor device includes first and second vertical transport field-effect transistor (VTFET) devices. Each of the first and second VTFET devices includes a bottom epitaxial layer, a plurality of channel fins formed on the bottom epitaxial layer, a first interlayer dielectric (ILD) layer formed between the channel fins, a high-? metal gate formed between the channel fins and the first ILD layer, a top epitaxial layer formed discretely on each of the channel fins, and a trench epitaxial layer formed continuously across the top epitaxial layer, a portion of the first ILD layer also being formed between the first and second VTFET device. The semiconductor device also includes a second ILD layer formed on the portion of the first ILD layer that is between the first and second VTFET devices, the second ILD layer separating the top epitaxial layers of the first and second VTFET devices.

Abstract: Provided is a stacked field-effect transistor (FET). The stacked FET comprises a top active region. The width of the top of the top active region is smaller than the width of bottom of the top active region. The stacked FET further comprises a top contact in direct contact with a top surface of the top active region. The stacked FET further comprises a bottom active region located substantially below the top active region. The stacked FET further comprises a bottom contact in direct contact with a top surface of the bottom active region. The bottom contact is wider at a top end than at a bottom end.

Abstract: Semiconductor device layout designs for Vt tuning are provided. In one aspect, a semiconductor device is provided. The semiconductor device includes: at least one first metal line in contact with a source or drain of an FET; at least one second metal line in contact with a gate of the FET, wherein the first metal line crosses the second metal line; and an oxygen diffusion blocking layer on top of the at least one first metal line in an overlap area of the at least one first metal line and the at least one second metal line. A method of forming a semiconductor device is also provided.

Abstract: A portable medical device includes a portable medical bag, a plurality of connectors and a processor. These connectors respectively connect the portable medical bag and every medical device contained inside the portable medical bag. The portable medical bag obtains the device management information of each the medical device through these connectors. The device management information includes the remaining power of medical device. The processor calculates the charge strategy information of the corresponding medical device according to the medical device information, address information and device management information. In addition, a management method for portable medical device is also provided.

Abstract: An interconnect layer for a device and methods for fabricating the interconnect layer are provided. The interconnect layer includes first metal structures arranged in a first array in the interconnect layer and second metal structures, arranged in a second array in the interconnect layer. The second array includes at least one metal structure positioned between two metal structures of the first metal structures. The interconnect layer also includes a spacer material formed around each of the first metal structures and the second metal structures and air gaps formed in the spacer material on each side of the first metal structures.

Abstract: A field effect device is provided. The field effect device includes a lower active gate structure on a substrate, and a first lower source/drain on a first side of the lower active gate structure. The field effect device further includes a second lower source/drain on a second side of the lower active gate structure opposite the first side, and a first lower source/drain contact interface on the first lower source/drain. The field effect device further includes a first upper source/drain on the first side of an upper active gate structure, and a second upper source/drain on the second side of the upper active gate structure opposite the first side. The field effect device further a shared source/drain contact forming an electrical connection between the first lower source/drain and the first upper source/drain; and a lower source/drain contact forming an electrical connection to the second lower source/drain.

Abstract: A semiconductor device comprises a substrate including at least one vertical fin extending from the substrate, a bottom source/drain region beneath the at least one vertical fin, a top source/drain region disposed above the at least one vertical fin, a metal gate structure, a contact coupled to the top source/drain region and first and second contact spacers disposed on each side of the contact.

Abstract: Semiconductor devices and methods of forming the same include forming dummy gate spacers in a trench in a semiconductor substrate. A dummy gate is formed in the trench. An exposed dummy gate spacer is replaced with a sacrificial spacer. A cap layer is formed over the dummy gate. The cap layer is etched to expose the dummy gate. The sacrificial spacer is replaced with an isolation dielectric spacer. The dummy gate is replaced with a conductor.

Abstract: The present disclosure relates to systems, non-transitory computer-readable media, and methods that utilize a deep neural network to process object user indicators and an initial object segmentation from a digital image to efficiently and flexibly generate accurate object segmentations. In particular, the disclosed systems can determine an initial object segmentation for the digital image (e.g., utilizing an object segmentation model or interactive selection processes). In addition, the disclosed systems can identify an object user indicator for correcting the initial object segmentation and generate a distance map reflecting distances between pixels of the digital image and the object user indicator. The disclosed systems can generate an image-interaction-segmentation triplet by combining the digital image, the initial object segmentation, and the distance map.

Abstract: A semiconductor device is presented that includes source/drain epitaxial regions disposed over a substrate, source/drain contacts (CA) disposed in direct contact with the source/drain epitaxial regions, where at least one of the CA contacts directly contacts a buried power rail or backside power rail through a via-to-BPR (VBPR) contact, a dielectric cap disposed over one or more of the CA contacts, and a local interconnect constructed in direct contact with one area of the dielectric cap such that a portion of the local interconnect is vertically aligned with the backside power rail. A backside power distribution network (BSPDN) is disposed adjacent the backside power rail.

Abstract: A method includes forming a p-type field effect transistor region and an n-type field effect transistor region into a semiconductor substrate. The method implements a process flow to fabricate highly doped top source/drains with minimal lithography and etching processes. The method permits the formation of VFETs with increased functionality and reduced scaling.

Abstract: One or more computing devices, systems, and/or methods for cross-domain action prediction are provided. Action sequence embeddings are generated based upon a textual embedding and a graph embedding utilizing past user action sequences corresponding to sequences of past actions performed by users across a plurality of domains. An autoencoder is trained to utilize the action sequence embeddings to project the action sequence embeddings to obtain intent space vectors. A service switch classifier is trained using the intent space vectors. In response to the service switch classifier predicting that a current user will switch from a current domain to a next domain, the current user is provided with a recommendation of an action corresponding to the next domain.

Abstract: Systems and methods for image processing are described. Embodiments of the present disclosure receive an image having a plurality of object instances; encode the image to obtain image features; decode the image features to obtain object features; generate object detection information based on the object features using an object detection branch, wherein the object detection branch is trained based on a first training set using a detection loss; generate semantic segmentation information based on the object features using a semantic segmentation branch, wherein the semantic segmentation branch is trained based on a second training set different from the first training set using a semantic segmentation loss; and combine the object detection information and the semantic segmentation information to obtain panoptic segmentation information that indicates which pixels of the image correspond to each of the plurality of object instances.