Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor structure in a first device region on a substrate, and forming a second vertical transistor structure in a second device region on the substrate. The first vertical transistor structure includes a first plurality of fins, and the second vertical transistor structure includes a second plurality of fins. A plurality of first source/drain regions are grown from upper portions of the first plurality of fins, and a contact liner layer is formed on the first source/drain regions. The method further includes forming a plurality of first silicide portions from the contact liner layer on the first source/drain regions, and forming a plurality of second silicide portions on a plurality of second source/drain regions extending from upper portions of the second plurality of fins. The second silicide portions have a different composition than the first silicide portions.

Abstract: A method is presented for forming a self-aligned middle-of-the-line (MOL) contact. The method includes forming a fin structure over a substrate, depositing and etching a first set of dielectric layers over the fin structure, etching the fin structure to form a sacrificial fin and a plurality of active fins, depositing a work function metal layer over the plurality of active fins, depositing an inter-layer dielectric (ILD) and a second set of dielectric layers. The method further includes etching the second set of dielectric layers and the ILD to form a first via portion and to expose a top surface of the sacrificial fin, removing the sacrificial fin to form a second via portion, and filling the first and second via portions with a conductive material to form the MOL contact in the first via portion and a contact landing in the second via portion.

Abstract: A method includes forming a p-type field effect transistor region and an n-type field effect transistor region into a semiconductor substrate. The method implements a process flow to fabricate highly doped top source/drains with minimal lithography and etching processes. The method permits the formation of VFETs with increased functionality and reduced scaling.

Abstract: A method for fabricating a semiconductor device includes forming top source/drain contact material on top source/drain material disposed on one or more fins of a base structure, and subtractively patterning the top source/drain contact material to form at least one top source/drain contact. The at least one top source/drain contact has a positive tapered geometry. The method further includes cutting exposed end portions of the top source/drain material to form at least one top source/drain region underneath the at least one top source/drain contact.

Abstract: A method for recognizing a gesture and gesture sensing apparatus are provided. When movement of an object is detected, a first energy sequence and a second energy sequence are generated. Then, whether signal patterns of the first energy sequence and the second energy sequence match is determined. After determining that the signal patterns of the first energy sequence match that of the second energy sequence, the first energy sequence and the second energy sequence are analyzed to obtain a corresponding gesture event.

Abstract: Provided are embodiments for an MOL interconnect structure having low metal-to-metal interface resistance interconnect structure including one or more contacts of one or more devices formed on a substrate. A dielectric layer is formed on one or more devices. One or more trenches are formed in the dielectric layer. The MOL interconnect structure also includes a barrier layer formed on one or more portions of the dielectric layer, along with a metallization layer, wherein the metallization layer forms a metal-to-metal interface with the one or more contacts.

Abstract: Semiconductor devices and methods of forming the same include forming a gate stack in contact with sidewalls of a semiconductor fin and on a bottom spacer over a bottom source/drain region. An encapsulating material is selectively deposited over the gate stack, leaving the bottom spacer exposed. An inter-layer dielectric is formed over the encapsulating material. A via is formed in the inter-layer dielectric to contact the bottom source/drain layer.

Abstract: A method of forming a semiconductor structure includes the following steps. At least a first source/drain region and a second source/drain region are formed in a substrate. At least a first sacrificial layer and a second sacrificial layer are respectively formed over the first source/drain region and the second source/drain region. A spacer layer is formed on at least a top surface of the substrate and around sides of the first sacrificial layer and the second sacrificial layer. The spacer layer includes an electrical-isolating material. The first sacrificial layer and a second sacrificial layer are removed to form a first open trench and a second open trench. The first open trench and the second open trench are filled with metal contact material to form a first metal contact and a second metal contact electrically isolated from each other by the spacer layer.

Abstract: A positioning guidance method for tooth brackets is provided. The positioning guidance method includes: obtaining, via an image capturing unit, an oral image; obtaining, via a processor, a position of a candidate tooth according to the contour of a plurality of teeth in the oral image; obtaining, via the processor, a bracket setting position corresponding to the candidate tooth by accessing dental model information from a storage device according to the position of the candidate tooth; obtaining, via the processor, a bracket image corresponding to a bracket from the oral image; and displaying, via the processor, guidance indication on a display unit according to a bracket position corresponding to the bracket image and the bracket setting position.

Abstract: A semiconductor device includes a first interconnect structure formed in an Mx level of the semiconductor device, the Mx level includes a third interlevel dielectric layer located above a second capping layer, a first trench within the third interlevel dielectric layer extending through the second capping layer to expose a top surface of a contact structure located below the second capping layer, the contact structure is located within a second interlevel dielectric layer, a second metal liner conformally deposited within the first trench, and a first seed layer conformally deposited above the second metal liner, the first seed layer includes a metal manganese film. A first thermal annealing process is conducted on the semiconductor device to form a first barrier liner underneath the second metal liner to prevent diffusion of conductive metals.

Abstract: A method includes applying a first dielectric material onto a semiconductor substrate to form a first dielectric layer on the semiconductor substrate, creating a plurality of openings in the dielectric layer, depositing a sacrificial material within the openings of the dielectric layer, removing the sacrificial material from at least a first segment of a first trench of the openings, depositing a second dielectric fill material into the first segment of the first trench opening where the sacrificial material was removed, removing the sacrificial material from at least some of the remaining openings and depositing a metallic material within the first trench opening to define at least first and second lines in the first trench and form a metallic interconnect structure.

Abstract: A method of forming stacked vertical field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first spacer layer on the substrate, a first protective liner on the first spacer layer, a first gap layer on the first protective liner, a second protective liner on the first gap layer, a second spacer layer on the second protective liner, a sacrificial layer on the second spacer layer, a third spacer layer on the sacrificial layer, a third protective liner on the third spacer layer, a second gap layer on the third protective liner, a fourth protective liner on the second gap layer, and a fourth spacer layer on the fourth protective liner. The method further includes forming channels through the layer stack, a liner layer on the sidewalls of the channels, and a vertical pillar in the channels.

Abstract: A method of forming stacked vertical field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first spacer layer on the substrate, a first protective liner on the first spacer layer, a first gap layer on the first protective liner, a second protective liner on the first gap layer, a second spacer layer on the second protective liner, a sacrificial layer on the second spacer layer, a third spacer layer on the sacrificial layer, a third protective liner on the third spacer layer, a second gap layer on the third protective liner, a fourth protective liner on the second gap layer, and a fourth spacer layer on the fourth protective liner. The method further includes forming channels through the layer stack, a liner layer on the sidewalls of the channels, and a vertical pillar in the channels.

Abstract: Various methods and structures for fabricating a semiconductor structure. The semiconductor structure includes in a top layer of a semiconductor stack a semiconductor contact located according to a first horizontal pitch. A first metallization layer is disposed directly on the top layer and includes a metallization contact located according to a second horizontal pitch, the second horizontal pitch being different from the first horizontal pitch such that the location of the metallization contact is vertically mismatched from the location of the semiconductor contact. A second metallization layer is disposed directly on the first metallization layer. The second metallization layer includes a super viabar structure that forms an electrical interconnect, in the second metallization layer, between the semiconductor contact in the top layer of the semiconductor stack and the metallization contact in the first metallization layer.

Abstract: MOL non-SAC structures and techniques for formation thereof are provided. In one aspect, a method of forming a semiconductor device includes: patterning fins in a substrate; forming gates over the fins and source/drains offset by gate spacers; lining upper sidewalls of the gates with a first dielectric liner; depositing a source/drain metal; lining upper sidewalls of the source/drain metal with a second dielectric liner; depositing a dielectric over the gates and source/drains; forming a first via in the dielectric which exposes the second dielectric liner over a select source/drain; removing the second dielectric liner from the select source/drain; forming a second via in the dielectric which exposes the first dielectric liner over a select gate; removing the first dielectric liner from the select gate; forming a source/drain contact in the first via; and forming a gate contact in the second via. A semiconductor device is also provided.

Abstract: Semiconductor structures fabricated via extreme ultraviolet (EUV) lithographic patterning techniques implementing directional deposition on a EUV resist mask improves selectivity and critical dimension control during the patterning of features in multiple layers of the semiconductor substrate. A semiconductor structure includes a substrate structure having an extreme ultraviolet resist mask disposed over one or more additional layers of the substrate structure. The extreme ultraviolet resist mask defines patterning features. A hard mask layer including a hard mask material is disposed on the extreme ultraviolet resist mask and covers the patterning features of the extreme ultraviolet resist mask.

Abstract: Gate contact over active layout designs are provided. In one aspect, a method for forming a gate contact over active device includes: forming a device including metal gates over an active area of a wafer, and source/drains on opposite sides of the metal gates offset by gate spacers; recessing the metal gates/gate spacers; forming etch-selective spacers on top of the recessed gate spacers; forming gate caps on top of the recessed metal gates; forming source/drain contacts on the source/drains; forming source/drain caps on top of the source/drain contacts, wherein the etch-selective spacers provide etch selectivity to the gate caps and source/drain caps; and forming a metal gate contact that extends through one of the gate caps, wherein the etch-selective spacers prevent gate-to-source drain shorting by the metal gate contact. Alternate etch-selective configurations are also provided including a claw-shaped source/drain cap design. A gate contact over active device is also provided.

Abstract: Embodiments of the invention are directed to a method and resulting structures for a semiconductor device having self-aligned contacts. In a non-limiting embodiment of the invention, a semiconductor fin is formed vertically extending from a bottom source/drain region of a substrate. A conductive gate is formed over a channel region of the semiconductor fin. A top source/drain region is formed on a surface of the semiconductor fin and a top metallization layer is formed on the top source/drain region. A dielectric cap is formed over the top metallization layer.

Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor structure in a first device region on a substrate, and forming a second vertical transistor structure in a second device region on the substrate. The first vertical transistor structure includes a first plurality of fins, and the second vertical transistor structure includes a second plurality of fins. A plurality of first source/drain regions are grown from upper portions of the first plurality of fins, and a contact liner layer is formed on the first source/drain regions. The method further includes forming a plurality of first silicide portions from the contact liner layer on the first source/drain regions, and forming a plurality of second silicide portions on a plurality of second source/drain regions extending from upper portions of the second plurality of fins. The second silicide portions have a different composition than the first silicide portions.

Abstract: A semiconductor includes a semiconductor substrate having a bottom source/drain region and a vertical semiconductor fin having a bottom end that contacts the semiconductor substrate. The semiconductor device further includes a top source/drain region on a top end of the vertical semiconductor. The top source/drain region is separated from the semiconductor substrate by the vertical semiconductor fin. The semiconductor device further includes an electrically conductive cap on an outer surface of the top source/drain region.