Abstract: Techniques for area scaling of contacts in VTFET devices are provided. In one aspect, a VTFET device includes: a fin(s); a bottom source/drain region at a base of the fin(s); a gate stack alongside the fin(s); a top source/drain region present at a top of the fin(s); a bottom source/drain contact to the bottom source/drain region; and a gate contact to the gate stack, wherein the bottom source drain and gate contacts each includes a top portion having a width W1CONTACT over a bottom portion having a width W2CONTACT, wherein W2CONTACT<W1CONTACT, and wherein a sidewall along the top portion is discontinuous with a sidewall along the bottom portion. The bottom portion having the width W2CONTACT is present alongside the gate stack and the top source/drain region. A method of forming a VTFET device is also provided.

Abstract: A method is presented for constructing a semiconductor device. The method includes forming a plurality of fins over a nanosheet stack and a substrate, forming spacers between the nanosheet stack and one or more of the plurality of fins, each spacer defining a different shape, forming gate spacers adjacent the plurality of fins, the gate spacers directly contacting the one or more of the plurality of fins having a spacer, forming a barrier spacer between a set of fins of the plurality of fins, the barrier spacer directly contacting a top surface of a shallow trench isolation (STI) region, forming n-type epitaxial regions between the plurality of fins, forming p-type epitaxy regions over the n-type epitaxial regions, and forming a first contact extending vertically through the semiconductor device adjacent the barrier spacer and extending laterally away from the barrier spacer to directly contact a sidewall of an n-type epitaxial region.

Abstract: A method is presented for forming a self-aligned middle-of-the-line (MOL) contact. The method includes forming a fin structure over a substrate, depositing and etching a first set of dielectric layers over the fin structure, etching the fin structure to form a sacrificial fin and a plurality of active fins, depositing a work function metal layer over the plurality of active fins, depositing an inter-layer dielectric (ILD) and a second set of dielectric layers. The method further includes etching the second set of dielectric layers and the ILD to form a first, via portion and to expose a top surface of the sacrificial fin, removing the sacrificial fin to form a second via portion, and filling the first and second via portions with a conductive material to form the MOL contact in the first via portion and a contact landing in the second via portion.

Abstract: A shock isolation cushion has two basal components and at least one shock isolation tier. The two basal components are disposed at an interval. The at least one shock isolation tier is disposed between the two basal components and is sequentially stacked from one of the two basal components to the other one of the two basal components. Wherein each of the at least one shock isolation tier has multiple shock isolation units. Each of the multiple shock isolation units has a supporting section and at least two buffering sections. The at least two buffering sections respectively extend from two opposite ends of the supporting section. Each of the at least two buffering sections is curved to form an opening between the buffering section and the supporting section.

Abstract: A stacked device is provided. The stacked device includes a reduced height active device layer, and a plurality of lower source/drain regions in the reduced height active device layer. The stacked device further includes a lower interlayer dielectric (ILD) layer on the plurality of lower source/drain regions, and a conductive trench spacer in the lower interlayer dielectric (ILD) layer, wherein the conductive trench spacer is adjacent to one of the plurality of lower source/drain regions. The stacked device further includes a top active device layer adjacent to the lower interlayer dielectric (ILD) layer, and an upper source/drain section in the top active device layer. The stacked device further includes a shared contact in electrical connection with the upper source/drain section, the conductive trench spacer, and the one of the plurality of lower source/drain regions.

Abstract: The present disclosure relates to systems, methods, and non-transitory computer-readable media that generates object masks for digital objects portrayed in digital images utilizing a detection-masking neural network pipeline. In particular, in one or more embodiments, the disclosed systems utilize detection heads of a neural network to detect digital objects portrayed within a digital image. In some cases, each detection head is associated with one or more digital object classes that are not associated with the other detection heads. Further, in some cases, the detection heads implement multi-scale synchronized batch normalization to normalize feature maps across various feature levels. The disclosed systems further utilize a masking head of the neural network to generate one or more object masks for the detected digital objects. In some cases, the disclosed systems utilize post-processing techniques to filter out low-quality masks.

Abstract: A CMOS (complementary metal-oxide semiconductor) device includes an n-channel metal-oxide semiconductor (NMOS) device, a p-channel metal-oxide semiconductor (PMOS) device, the NMOS and the PMOS device surrounded by a first dielectric material, the NMOS device separated from the PMOS device by a second dielectric material, a first NMOS gate separated from a first PMOS gate by the second dielectric material, a second NMOS gate electrically connected to a second PMOS gate by a metal link disposed between the NMOS gate and the PMOS gate, the metal link disposed above the second dielectric material, a first source/drain (S/D) contact disposed above the second dielectric material, the first S/D contact disposed in contact with both NMOS S/D region and a PMOS S/D region, and a second S/D contact disposed adjacent to the second dielectric material, the second S/D contact disposed in contact with a single S/D region.

Abstract: Various disclosed embodiments are directed to refining or correcting individual semantic segmentation/instance segmentation masks that have already been produced by baseline models in order to generate a final coherent panoptic segmentation map. Specifically, a refinement model, such as an encoder-decoder-based neural network, generates or predicts various data objects, such as foreground masks, bounding box offset maps, center maps, center offset maps, and coordinate convolution. This, among other functionality described herein, improves the inaccuracies and computing resource consumption of existing technologies.

Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor structure in a first device region on a substrate, and forming a second vertical transistor structure in a second device region on the substrate. The first vertical transistor structure includes a first plurality of fins, and the second vertical transistor structure includes a second plurality of fins. A plurality of first source/drain regions are grown from upper portions of the first plurality of fins, and a contact liner layer is formed on the first source/drain regions. The method further includes forming a plurality of first silicide portions from the contact liner layer on the first source/drain regions, and forming a plurality of second silicide portions on a plurality of second source/drain regions extending from upper portions of the second plurality of fins. The second silicide portions have a different composition than the first silicide portions.

Abstract: Embodiments disclosed herein describe methods of forming semiconductor devices. The methods may include etching vias and trenches in a middle-of-line (MOL) layer that has a low-k dielectric layer, a sacrificial nitride layer, and a hard mask layer. The methods may also include depositing a thin nitride layer within the via trench, depositing a carbon layer on the thin nitride layer within the vias and trenches, etching back the thin nitride layer to expose a portion of the hard mask layer, removing the hard mask layer and the carbon layer, and removing the thin nitride layer and the sacrificial nitride layer.

Abstract: A device includes: a first dielectric material; a first metal line in the first dielectric material; a second dielectric material disposed on the first dielectric material and the first metal line; a second metal line in the second dielectric material; and a plurality of metal vias disposed on a same level and connecting the first metal line and the second metal line, wherein the plurality of metal vias comprise a first top via and a bottom via having different sidewall profile angles.

Abstract: A method includes forming a p-type field effect transistor region and an n-type field effect transistor region into a semiconductor substrate. The method implements a process flow to fabricate highly doped top source/drains with minimal lithography and etching processes. The method permits the formation of VFETs with increased functionality and reduced scaling.

Abstract: A semiconductor device includes first and second vertical transport field-effect transistor (VTFET) devices. Each of the first and second VTFET devices includes a bottom epitaxial layer, a plurality of channel fins formed on the bottom epitaxial layer, a first interlayer dielectric (ILD) layer formed between the channel fins, a high-? metal gate formed between the channel fins and the first ILD layer, a top epitaxial layer formed discretely on each of the channel fins, and a trench epitaxial layer formed continuously across the top epitaxial layer, a portion of the first ILD layer also being formed between the first and second VTFET device. The semiconductor device also includes a second ILD layer formed on the portion of the first ILD layer that is between the first and second VTFET devices, the second ILD layer separating the top epitaxial layers of the first and second VTFET devices.

Abstract: A semiconductor structure and a method of making the same includes a first recessed region in a semiconductor structure, the first recessed region defining a first opening with a first positive tapering profile, as at least part of the first positive tapering profile, widening the first opening in a direction towards a top source/drain region of the semiconductor structure at a first tapering angle, and a top source/drain contact within the first opening, the top source/drain contact surrounding a surface of the top source/drain region. The semiconductor structure further includes a protective liner located at an interface between a bottom portion of the top source/drain region, a top spacer adjacent to the top source/drain region and a dielectric material between two consecutive top source/drain regions, the protective liner protects the top source/drain regions during contact patterning.

Abstract: A semiconductor device containing a self-aligned contact rail is provided. The self-aligned contact rail can have a reduced critical dimension, CD. The self-aligned contact rail can be obtained utilizing a sacrificial semiconductor fin as a placeholder structure for the contact rail. The used of the sacrificial semiconductor fin enables reduced, and more controllable, CDs.

Abstract: An alarm detection device includes: a sound receiver for receiving an external sound to output a first signal; a signal processing circuit coupled to the sound receiver, for receiving the first signal to output a second signal; and an alarm decision circuit coupled to the signal processing circuit, during a time range, when a number of the second signals meeting a trigger criteria is equal to a predetermined value, the alarm decision circuit outputting an alarm signal.

Abstract: Methods are presented for forming multi-threshold field effect transistors. The methods generally include depositing and patterning an organic planarizing layer to protect underlying structures formed in a selected one of the nFET region and the pFET region of a semiconductor wafer. In the other one of the nFET region and the pFET region, structures are processed to form an undercut in the organic planarizing layer. The organic planarizing layer is subjected to a reflow process to fill the undercut. The methods are effective to protect a boundary between the nFET region and the pFET region.

Abstract: One or more computing devices, systems, and/or methods for cross-domain action prediction are provided. Action sequence embeddings are generated based upon a textual embedding and a graph embedding utilizing past user action sequences corresponding to sequences of past actions performed by users across a plurality of domains. An autoencoder is trained to utilize the action sequence embeddings to project the action sequence embeddings to obtain intent space vectors. A service switch classifier is trained using the intent space vectors. In response to the service switch classifier predicting that a current user will switch from a current domain to a next domain, the current user is provided with a recommendation of an action corresponding to the next domain.

Abstract: A semiconductor device comprising at least one first gate all around channel having a horizontal physical orientation, wherein the at least one first gate all around channel is comprised of a first material, wherein the at least one first gate all around channel has a sidewall surface with (100) crystal orientation. At least one second gate all around channel having a vertical physical orientation, wherein the second channel is located above the at least one first gate all around channel, wherein the at least one second gate all around channel is comprised of a second material, wherein the at least one second gate all around channel has a sidewall surface with (110) crystal orientation. A gate metal enclosing the at least one first gate all around channel and the at least one second gate all around channel.

Abstract: A memory device includes two phase change memory (PCM) cells and a bridge. The first PCM cell includes an electrical input and a phase change material. The second PCM cell includes an electrical input that is independent from the electrical input of the first PCM cell and another phase change material. The bridge is electrically connected to the two PCM cells.