Abstract: A method includes etching a gate stack to form a trench extending through the gate stack, the gate stack including a metal gate electrode and a gate dielectric, wherein forming the trench removes a portion of the gate stack to separate the gate stack into a first gate stack portion and a second gate stack portion; extending the trench through an isolation region under the gate stack and into a semiconductor substrate under the isolation region; conformally depositing a first dielectric material on surfaces in the trench; and depositing a second dielectric material on the first dielectric material to fill the trench, wherein the first dielectric material is a more flexible material than the second dielectric material.

Abstract: A wafer treatment system is provided. The wafer treatment system includes a wafer treatment chamber defining a treatment area within which a wafer is treated. The wafer treatment system includes a gas injection system. The gas injection system includes a gas injector configured to inject a first gas, used for treatment of the wafer, into the treatment area. A first gas tube is configured to conduct the first gas at a first temperature to the gas injector. The gas injection system includes a heating enclosure enclosing the gas injector. A second gas tube is configured to conduct a heated gas to the heating enclosure to increase an enclosure temperature at the heating enclosure to a second enclosure temperature. A temperature of the first gas is increased in the gas injector from the first temperature to a second temperature due to the second enclosure temperature at the heating enclosure.

Abstract: A wafer treatment system is provided. The wafer treatment system includes a wafer treatment chamber defining a treatment area within which a wafer is treated. The wafer treatment system includes a gas injection system. The gas injection system includes a gas injector configured to inject a first gas, used for treatment of the wafer, into the treatment area. A first gas tube is configured to conduct the first gas at a first temperature to the gas injector. The gas injection system includes a heating enclosure enclosing the gas injector. A second gas tube is configured to conduct a heated gas to the heating enclosure to increase an enclosure temperature at the heating enclosure to a second enclosure temperature. A temperature of the first gas is increased in the gas injector from the first temperature to a second temperature due to the second enclosure temperature at the heating enclosure.

Abstract: A system and method for cleaning a preclean process chamber in between wafer processing. The internal pressure of the preclean process chamber is reduced to a first pressure and a first gas that consists of oxygen and an inert or noble gas, is introduced into the chamber. Plasma is generated within the preclean process chamber using the first gas at the first pressure. Internal pressure is then reduced to a second pressure, less than the first, and the first gas is continued into the chamber. Plasma is then generated using the first gas at the second pressure. Thereafter, a second gas, consisting of an oxygen-free inert or noble gas, is introduced into the chamber at the second pressure, following which plasma is generated within the chamber using only the second gas.

Abstract: A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.

Abstract: Embodiments of the present disclosure provide a cryogenic pump for semiconductor processing, including a body having a flange, configured to be coupled to a process chamber, and an opening defined at a first end of the body; one or more capture plate modules disposed in the body; and a cold header thermally coupled to the one or more capture plate modules. A longitudinal axis of the body is defined from the first end of the body to a second end of the body. A first lateral dimension of the opening is less than a second lateral dimension of the body, the first and second lateral dimensions being defined perpendicular to the longitudinal axis. The second lateral dimension is defined at a position between the opening and the second end.

Abstract: A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.

Abstract: The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot; performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.

Abstract: A method of manufacturing a semiconductor device is as below. An exposed photoresist layer is developed using a developer supplied by a developer supplying unit. An ammonia gas by-product of the developer is discharged through a gas outlet of the developer supplying unit into a treating tool. The ammonia gas by-product is retained in the treating tool. A concentration of the ammonia gas by-product is monitored.

Abstract: An image sensor includes a substrate, a grid, and a color filter. The grid is over the substrate. From a cross-sectional view, the grid includes a first grid and a second grid over the first grid, the first grid has lower portion that has a first sidewall and a second sidewall opposing the first sidewall, the second grid has a third sidewall and a fourth sidewall opposing the third sidewall, and a width between the third sidewall and the fourth sidewall is less than a width between the first sidewall and the second sidewall. The color filter extends through the grid structure.

Abstract: The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot; performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.

Abstract: A method includes sequentially depositing a floating gate layer, a dielectric structure stack, and a control gate layer over a substrate. A first etching process is performed to pattern the control gate layer, the dielectric structure stack, and a top portion of the floating gate layer to form a control gate, a dielectric structure, and a top portion of a floating gate over a bottom portion of the floating gate layer. A sidewall of the top portion of the floating gate is concave. A first spacer structure is formed on the sidewall of the top portion of the floating gate, a sidewall of the dielectric structure, and a sidewall of the control gate. A second etching process is performed to pattern the bottom portion of the floating gate layer to form a bottom portion of the floating gate after forming the first spacer structure.

Abstract: A method includes depositing a gate dielectric film over a substrate. A floating gate layer and a control gate layer are deposited over the gate dielectric film. The control gate layer is patterned to form a control gate over the floating gate layer. A top portion of the floating gate layer is patterned. A spacer structure is formed on a sidewall of the control gate and over a remaining portion of the floating gate layer. The remaining portion of the floating gate layer is patterned to form a bottom portion of a floating gate. A ratio of the bottom width of the bottom portion to the middle width of the bottom portion is in a range between about 103% and about 108%. The gate dielectric film is patterned form a gate dielectric layer.

Abstract: In a method for forming a semiconductor device photo-sensing regions are formed over a frontside of a substrate. A first layer is formed over a backside of the substrate and is patterned to form a plurality of grid lines. The grid lines can define a plurality of first areas and a plurality of second areas. A second layer may be formed over exposed portions of the backside, the gridlines, the first areas, and the second areas and a third layer may be formed over the second layer. The second and third layer may have different etch rates and the third layer is pattern so as to remove the third layer from over the plurality of first areas.

Abstract: A method incudes forming a plurality of photodiodes in a substrate; forming an interconnect structure on a front-side of the substrate; forming a barrier layer on a back-side of the substrate; depositing a metal layer over the barrier layer; forming an adhesion enhancement layer over the metal layer; forming an oxide layer over the adhesion enhancement layer; etching the oxide layer, the adhesion enhancement layer, the metal layer, and the barrier layer to form an oxide grid, an adhesion enhancement grid, a metal grid, and a barrier grid, respectively, wherein the barrier grid and the adhesion enhancement grid have a same chemical element.

Abstract: A system and method for cleaning a preclean process chamber in between wafer processing. The internal pressure of the preclean process chamber is reduced to a first pressure and a first gas that consists of oxygen and an inert or noble gas, is introduced into the chamber. Plasma is generated within the preclean process chamber using the first gas at the first pressure. Internal pressure is then reduced to a second pressure, less than the first, and the first gas is continued into the chamber. Plasma is then generated using the first gas at the second pressure. Thereafter, a second gas, consisting of an oxygen-free inert or noble gas, is introduced into the chamber at the second pressure, following which plasma is generated within the chamber using only the second gas.

Abstract: Methods of forming a semiconductor device structure are described. The method includes forming a first conductive feature including a conductive fill material over a substrate, forming an etch stop layer on the conductive fill material, forming an intermetallization dielectric on the etch stop layer, forming an opening in the etch stop layer and the intermetallization dielectric to expose a portion of the conductive fill material, forming a recess in the exposed portion of the conductive fill material, and the opening and the recess together form a rivet-shaped space. The method further includes forming a second conductive feature in the rivet-shaped space and forming a metal nitride layer over the intermetallization dielectric and the second conductive feature. The forming the metal nitride layer includes depositing the metal nitride layer and treating the metal nitride layer with a plasma treatment process.

Abstract: An image sensor structure includes a semiconductor device, a plurality of image sensing elements formed in the semiconductor substrate, an interconnect structure formed on the semiconductor substrate, and a composite grid structure over the semiconductor substrate. The composite grid structure includes a tungsten grid, an oxide grid over the tungsten grid, and an adhesion enhancement grid spacing the tungsten grid from the oxide grid.

Abstract: The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot, performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.

Abstract: A method of manufacturing a semiconductor device is as below. An exposed photoresist layer is developed using a developer supplied by a developer supplying unit. An ammonia gas by-product of the developer is discharged through a gas outlet of the developer supplying unit into a treating tool. The ammonia gas by-product is retained in the treating tool. A concentration of the ammonia gas by-product is monitored.