Patents by Inventor Su-Yu Yeh

Su-Yu Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11282931
    Abstract: A memory device includes a floating gate, a control gate, a spacer structure, a dielectric layer, and an erase gate. The floating gate is above a substrate. The floating gate has a curved sidewall. The control gate is above the floating gate. The spacer structure is in contact with the control gate and the floating gate. The spacer structure is spaced apart from the curved sidewall of the floating gate. The dielectric layer is in contact with the spacer structure and the curved sidewall of the floating gate. The erase gate is above the dielectric layer.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chu Lin, Chi-Chung Jen, Chia-Ming Pan, Su-Yu Yeh, Keng-Ying Liao, Chih-Wei Sung
  • Publication number: 20210408023
    Abstract: The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot, performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.
    Type: Application
    Filed: June 30, 2020
    Publication date: December 30, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Y.J. WU, Chih-Ming LEE, Keng-Ying LIAO, Ping-Pang Hsieh, Su-Yu YEH, H.H. LIN, Y.L. WANG
  • Publication number: 20210351225
    Abstract: In a method for forming a semiconductor device photo-sensing regions are formed over a frontside of a substrate. A first layer is formed over a backside of the substrate and is patterned to form a plurality of grid lines. The grid lines can define a plurality of first areas and a plurality of second areas. A second layer maybe formed over exposed portions of the backside, the gridlines, the first areas, and the second areas and a third layer may be formed over the second layer. The second and third layer may have different etch rates and the third layer is pattern so as to remove the third layer from over the plurality of first areas.
    Type: Application
    Filed: July 19, 2021
    Publication date: November 11, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO.
    Inventors: H. L. CHEN, Huai-jen TUNG, Keng-Ying LIAO, Po-Zen CHEN, Su-Yu YEH, Chih Wei SUNG
  • Publication number: 20210341843
    Abstract: A method of manufacturing a semiconductor device and a semiconductor processing system are provided. The method includes the following steps. A photoresist layer is formed on a substrate in a lithography tool. The photoresist layer is exposed in the lithography tool to form an exposed photoresist layer. The exposed photoresist layer is developed to form a patterned photoresist layer in the lithography tool by using a developer. An ammonia gas by-product of the developer is removed from the lithography tool.
    Type: Application
    Filed: July 12, 2021
    Publication date: November 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Kai Chen, Chia-Hung Chung, Ko-Bin Kao, Su-Yu Yeh, Li-Jen Wu, Zhi-You Ke, Ming-Hung Lin
  • Patent number: 11164903
    Abstract: The present disclosure describes the formation of a pad structure in an image sensor device using a sacrificial isolation region and a silicon oxide based stack with no intervening nitride etch-stop layers. The image sensor device includes a semiconductor layer comprising a first horizontal surface opposite to a second horizontal surface; a metallization layer formed on the second horizontal surface of the semiconductor layer, where the metallization layer includes a dielectric layer. The image sensor device also includes a pad region traversing through the semiconductor layer from the first horizontal surface to the second horizontal surface. The pad region includes an oxide layer with no intervening nitride layers formed on the dielectric layer of the metallization layer and a pad structure in physical contact with a conductive structure of the metallization layer.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: November 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huai-jen Tung, Ching-Chung Su, Keng-Ying Liao, Po-Zen Chen, Su-Yu Yeh, S. Y. Chen
  • Publication number: 20210249232
    Abstract: An apparatus includes a chamber, a pedestal configured to receive and support a semiconductor wafer in the chamber, and an edge ring disposed over the pedestal. The edge ring includes a first portion having a first top surface, a second portion coupled to the first portion and having a second top surface lower than the first top surface, and a recess defined in the first portion. The second top surface is under the semiconductor wafer. The recess has a depth, and a distance between the pedestal and an inner surface of the recess is substantially equal to the depth of the recess.
    Type: Application
    Filed: February 10, 2020
    Publication date: August 12, 2021
    Inventors: HUNG-BIN LIN, LI-CHAO YIN, SHIH-TSUNG CHEN, YU-LUNG YANG, YING CHIEH WANG, BING KAI HUANG, SU-YU YEH
  • Publication number: 20210225918
    Abstract: An image sensor structure includes a semiconductor device, a plurality of image sensing elements formed in the semiconductor substrate, an interconnect structure formed on the semiconductor substrate, and a composite grid structure over the semiconductor substrate. The composite grid structure includes a tungsten grid, an oxide grid over the tungsten grid, and an adhesion enhancement grid spacing the tungsten grid from the oxide grid.
    Type: Application
    Filed: January 17, 2020
    Publication date: July 22, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Yu LIN, Keng-Ying LIAO, Su-Yu YEH, Po-Zen CHEN, Huai-Jen TUNG, Hsien-Li CHEN
  • Patent number: 11069740
    Abstract: In a method for forming a semiconductor device photo-sensing regions are formed over a frontside of a substrate. A first layer is formed over a backside of the substrate and is patterned to form a plurality of grid lines. The grid lines can define a plurality of first areas and a plurality of second areas. A second layer maybe formed over exposed portions of the backside, the gridlines, the first areas, and the second areas and a third layer may be formed over the second layer. The second and third layer may have different etch rates and the third layer is pattern so as to remove the third layer from over the plurality of first areas.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: July 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: H. L. Chen, Huai-jen Tung, Keng-Ying Liao, Po-Zen Chen, Su-Yu Yeh, Chih Wei Sung
  • Patent number: 11061333
    Abstract: A method of manufacturing a semiconductor device and a semiconductor processing system are provided. The method includes the following steps. A photoresist layer is formed on a substrate in a lithography tool. The photoresist layer is exposed in the lithography tool to form an exposed photoresist layer. The exposed photoresist layer is developed to form a patterned photoresist layer in the lithography tool by using a developer. An ammonia gas by-product of the developer is removed from the lithography tool.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Kai Chen, Chia-Hung Chung, Ko-Bin Kao, Su-Yu Yeh, Li-Jen Wu, Zhi-You Ke, Ming-Hung Lin
  • Patent number: 11029603
    Abstract: Embodiments of the present disclosure describe a chemical replacement system and a method to automatically replace PR bottles. The chemical replacement system includes a computer system and a transfer module. The computer system can receive a request signal to replace one or more chemical containers and transmit a command to the transfer module. The transfer module, being controlled by the computer system, can include a holder configured to hold the one or more chemical containers (e.g., PR bottles); a door unit configured to open in response to the command; and a transfer unit configured to eject the holder in response to the command for replacement. The chemical replacement system can further include an automated vehicle configured to replace the one or more chemical containers in the ejected holder.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu Kai Chen, Forster Yuan, Ko-Bin Kao, Shi-Ming Wang, Su-Yu Yeh, Li-Jen Wu, Oliver Yu
  • Patent number: 11004709
    Abstract: A method for monitoring gas in a wafer processing system is provided. The method includes producing an exhaust flow in an exhausting conduit from a processing chamber. The method further includes placing a gas sensor in fluid communication with a detection point located in the exhausting conduit via a sampling tube that passes through a through hole formed on the exhausting conduit. The detection point is located away from the through hole. The method also includes detecting a gas condition at the detection point with the gas sensor. In addition, the method also includes analyzing the gas condition detected by the gas sensor to determine if the gas condition in the exhausting conduit is in a range of values.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: May 11, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Chieh Hsieh, Su-Yu Yeh, Ko-Bin Kao, Chia-Hung Chung, Li-Jen Wu, Chun-Yu Chen, Hung-Ming Chen, Yong-Ting Wu
  • Patent number: 10943802
    Abstract: The present disclosure describes a container for placing an object therein. The container includes a container body and a lid over the container body, a collision-preventing portion attached to one or more of the container body and the lid and configured to buffer an impact force, a pairing recognition mechanism configured to detect an object placed in the container body, and a liquid-detecting sensor configured to detect a leakage from the object.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu Kai Chen, Chia-Hung Chung, Ko-Bin Kao, Shi-Ming Wang, Su-Yu Yeh, Li-Jen Wu, Oliver Yu, Wen-Shiung Chen
  • Publication number: 20210036118
    Abstract: A memory device includes a floating gate, a control gate, a spacer structure, a dielectric layer, and an erase gate. The floating gate is above a substrate. The floating gate has a curved sidewall. The control gate is above the floating gate. The spacer structure is in contact with the control gate and the floating gate. The spacer structure is spaced apart from the curved sidewall of the floating gate. The dielectric layer is in contact with the spacer structure and the curved sidewall of the floating gate. The erase gate is above the dielectric layer.
    Type: Application
    Filed: May 20, 2020
    Publication date: February 4, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chu LIN, Chi-Chung JEN, Chia-Ming PAN, Su-Yu YEH, Keng-Ying LIAO, Chih-Wei SUNG
  • Publication number: 20210036179
    Abstract: A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.
    Type: Application
    Filed: May 4, 2020
    Publication date: February 4, 2021
    Inventors: Chih Wei Sung, Chung-Bin Tseng, Keng-Ying Liao, Yen-Jou Wu, Po-Zen Chen, Su-Yu Yeh, Ching-Chung Su
  • Publication number: 20210020669
    Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a metal catalyst layer on an etching area of the semiconductor substrate; performing a wet etch process to the semiconductor substrate to etch the etching area of the semiconductor substrate under the metal catalyst layer, thereby forming a trench in the semiconductor substrate; and removing the metal catalyst layer from the semiconductor substrate after performing the wet etch process.
    Type: Application
    Filed: July 15, 2019
    Publication date: January 21, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Yu LIN, Keng-Ying LIAO, Huai-Jen TUNG, Po-Zen CHEN, Su-Yu YEH, Chia-Yun CHEN, Ta-Cheng WEI
  • Patent number: 10879289
    Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a metal catalyst layer on an etching area of the semiconductor substrate; performing a wet etch process to the semiconductor substrate to etch the etching area of the semiconductor substrate under the metal catalyst layer, thereby forming a trench in the semiconductor substrate; and removing the metal catalyst layer from the semiconductor substrate after performing the wet etch process.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Yu Lin, Keng-Ying Liao, Huai-Jen Tung, Po-Zen Chen, Su-Yu Yeh, Chia-Yun Chen, Ta-Cheng Wei
  • Patent number: 10872873
    Abstract: A method is provided and includes the following steps. A first wafer is coupled to a first support of a bonding tool and a second wafer is coupled to a second support of the bonding tool. The second wafer is bonded to the first wafer with the first wafer coupled to the first support. Whether a bubble is between the bonded first and second wafers in the bonding tool is detected.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Chih Chen, Tsung-Yi Yang, Chung-I Hung, Mu-Han Cheng, Tzu-Shin Chen, Su-Yu Yeh
  • Publication number: 20200373344
    Abstract: The present disclosure describes the formation of a pad structure in an image sensor device using a sacrificial isolation region and a silicon oxide based stack with no intervening nitride etch-stop layers. The image sensor device includes a semiconductor layer comprising a first horizontal surface opposite to a second horizontal surface; a metallization layer formed on the second horizontal surface of the semiconductor layer, where the metallization layer includes a dielectric layer. The image sensor device also includes a pad region traversing through the semiconductor layer from the first horizontal surface to the second horizontal surface. The pad region includes an oxide layer with no intervening nitride layers formed on the dielectric layer of the metallization layer and a pad structure in physical contact with a conductive structure of the metallization layer.
    Type: Application
    Filed: May 24, 2019
    Publication date: November 26, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huai-jen TUNG, Ching-Chung SU, Keng-Ying LIAO, Po-Zen CHEN, Su-Yu YEH, S.Y. CHEN
  • Publication number: 20200279887
    Abstract: In a method for forming a semiconductor device photo-sensing regions are formed over a frontside of a substrate. A first layer is formed over a backside of the substrate and is patterned to form a plurality of grid lines. The grid lines can define a plurality of first areas and a plurality of second areas. A second layer maybe formed over exposed portions of the backside, the gridlines, the first areas, and the second areas and a third layer may be formed over the second layer. The second and third layer may have different etch rates and the third layer is pattern so as to remove the third layer from over the plurality of first areas.
    Type: Application
    Filed: February 28, 2019
    Publication date: September 3, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co.
    Inventors: H. L. Chen, Huai-jen Tung, Keng-Ying Liao, Po-Zen Chen, Su-Yu Yeh, Chih Wei Sung
  • Publication number: 20200103756
    Abstract: Embodiments of the present disclosure describe a chemical replacement system and a method to automatically replace PR bottles. The chemical replacement system includes a computer system and a transfer module. The computer system can receive a request signal to replace one or more chemical containers and transmit a command to the transfer module. The transfer module, being controlled by the computer system, can include a holder configured to hold the one or more chemical containers (e.g., PR bottles); a door unit configured to open in response to the command; and a transfer unit configured to eject the holder in response to the command for replacement. The chemical replacement system can further include an automated vehicle configured to replace the one or more chemical containers in the ejected holder.
    Type: Application
    Filed: December 19, 2018
    Publication date: April 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu Kai CHEN, Forster Yuan, Ko-BIn Kao, Shi-Ming Wang, Su-Yu Yeh, Li-Jen Wu, Oliver Yu