Patents by Inventor Su-Yu Yeh
Su-Yu Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11029603Abstract: Embodiments of the present disclosure describe a chemical replacement system and a method to automatically replace PR bottles. The chemical replacement system includes a computer system and a transfer module. The computer system can receive a request signal to replace one or more chemical containers and transmit a command to the transfer module. The transfer module, being controlled by the computer system, can include a holder configured to hold the one or more chemical containers (e.g., PR bottles); a door unit configured to open in response to the command; and a transfer unit configured to eject the holder in response to the command for replacement. The chemical replacement system can further include an automated vehicle configured to replace the one or more chemical containers in the ejected holder.Type: GrantFiled: December 19, 2018Date of Patent: June 8, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu Kai Chen, Forster Yuan, Ko-Bin Kao, Shi-Ming Wang, Su-Yu Yeh, Li-Jen Wu, Oliver Yu
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Patent number: 11004709Abstract: A method for monitoring gas in a wafer processing system is provided. The method includes producing an exhaust flow in an exhausting conduit from a processing chamber. The method further includes placing a gas sensor in fluid communication with a detection point located in the exhausting conduit via a sampling tube that passes through a through hole formed on the exhausting conduit. The detection point is located away from the through hole. The method also includes detecting a gas condition at the detection point with the gas sensor. In addition, the method also includes analyzing the gas condition detected by the gas sensor to determine if the gas condition in the exhausting conduit is in a range of values.Type: GrantFiled: September 11, 2018Date of Patent: May 11, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Chieh Hsieh, Su-Yu Yeh, Ko-Bin Kao, Chia-Hung Chung, Li-Jen Wu, Chun-Yu Chen, Hung-Ming Chen, Yong-Ting Wu
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Patent number: 10943802Abstract: The present disclosure describes a container for placing an object therein. The container includes a container body and a lid over the container body, a collision-preventing portion attached to one or more of the container body and the lid and configured to buffer an impact force, a pairing recognition mechanism configured to detect an object placed in the container body, and a liquid-detecting sensor configured to detect a leakage from the object.Type: GrantFiled: December 27, 2018Date of Patent: March 9, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu Kai Chen, Chia-Hung Chung, Ko-Bin Kao, Shi-Ming Wang, Su-Yu Yeh, Li-Jen Wu, Oliver Yu, Wen-Shiung Chen
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Publication number: 20210036118Abstract: A memory device includes a floating gate, a control gate, a spacer structure, a dielectric layer, and an erase gate. The floating gate is above a substrate. The floating gate has a curved sidewall. The control gate is above the floating gate. The spacer structure is in contact with the control gate and the floating gate. The spacer structure is spaced apart from the curved sidewall of the floating gate. The dielectric layer is in contact with the spacer structure and the curved sidewall of the floating gate. The erase gate is above the dielectric layer.Type: ApplicationFiled: May 20, 2020Publication date: February 4, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Chu LIN, Chi-Chung JEN, Chia-Ming PAN, Su-Yu YEH, Keng-Ying LIAO, Chih-Wei SUNG
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Publication number: 20210036179Abstract: A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.Type: ApplicationFiled: May 4, 2020Publication date: February 4, 2021Inventors: Chih Wei Sung, Chung-Bin Tseng, Keng-Ying Liao, Yen-Jou Wu, Po-Zen Chen, Su-Yu Yeh, Ching-Chung Su
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Publication number: 20210020669Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a metal catalyst layer on an etching area of the semiconductor substrate; performing a wet etch process to the semiconductor substrate to etch the etching area of the semiconductor substrate under the metal catalyst layer, thereby forming a trench in the semiconductor substrate; and removing the metal catalyst layer from the semiconductor substrate after performing the wet etch process.Type: ApplicationFiled: July 15, 2019Publication date: January 21, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Yu LIN, Keng-Ying LIAO, Huai-Jen TUNG, Po-Zen CHEN, Su-Yu YEH, Chia-Yun CHEN, Ta-Cheng WEI
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Patent number: 10879289Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a metal catalyst layer on an etching area of the semiconductor substrate; performing a wet etch process to the semiconductor substrate to etch the etching area of the semiconductor substrate under the metal catalyst layer, thereby forming a trench in the semiconductor substrate; and removing the metal catalyst layer from the semiconductor substrate after performing the wet etch process.Type: GrantFiled: July 15, 2019Date of Patent: December 29, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Yu Lin, Keng-Ying Liao, Huai-Jen Tung, Po-Zen Chen, Su-Yu Yeh, Chia-Yun Chen, Ta-Cheng Wei
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Patent number: 10872873Abstract: A method is provided and includes the following steps. A first wafer is coupled to a first support of a bonding tool and a second wafer is coupled to a second support of the bonding tool. The second wafer is bonded to the first wafer with the first wafer coupled to the first support. Whether a bubble is between the bonded first and second wafers in the bonding tool is detected.Type: GrantFiled: January 12, 2018Date of Patent: December 22, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Chih Chen, Tsung-Yi Yang, Chung-I Hung, Mu-Han Cheng, Tzu-Shin Chen, Su-Yu Yeh
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Publication number: 20200373344Abstract: The present disclosure describes the formation of a pad structure in an image sensor device using a sacrificial isolation region and a silicon oxide based stack with no intervening nitride etch-stop layers. The image sensor device includes a semiconductor layer comprising a first horizontal surface opposite to a second horizontal surface; a metallization layer formed on the second horizontal surface of the semiconductor layer, where the metallization layer includes a dielectric layer. The image sensor device also includes a pad region traversing through the semiconductor layer from the first horizontal surface to the second horizontal surface. The pad region includes an oxide layer with no intervening nitride layers formed on the dielectric layer of the metallization layer and a pad structure in physical contact with a conductive structure of the metallization layer.Type: ApplicationFiled: May 24, 2019Publication date: November 26, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Huai-jen TUNG, Ching-Chung SU, Keng-Ying LIAO, Po-Zen CHEN, Su-Yu YEH, S.Y. CHEN
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Publication number: 20200279887Abstract: In a method for forming a semiconductor device photo-sensing regions are formed over a frontside of a substrate. A first layer is formed over a backside of the substrate and is patterned to form a plurality of grid lines. The grid lines can define a plurality of first areas and a plurality of second areas. A second layer maybe formed over exposed portions of the backside, the gridlines, the first areas, and the second areas and a third layer may be formed over the second layer. The second and third layer may have different etch rates and the third layer is pattern so as to remove the third layer from over the plurality of first areas.Type: ApplicationFiled: February 28, 2019Publication date: September 3, 2020Applicant: Taiwan Semiconductor Manufacturing Co.Inventors: H. L. Chen, Huai-jen Tung, Keng-Ying Liao, Po-Zen Chen, Su-Yu Yeh, Chih Wei Sung
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Publication number: 20200103756Abstract: Embodiments of the present disclosure describe a chemical replacement system and a method to automatically replace PR bottles. The chemical replacement system includes a computer system and a transfer module. The computer system can receive a request signal to replace one or more chemical containers and transmit a command to the transfer module. The transfer module, being controlled by the computer system, can include a holder configured to hold the one or more chemical containers (e.g., PR bottles); a door unit configured to open in response to the command; and a transfer unit configured to eject the holder in response to the command for replacement. The chemical replacement system can further include an automated vehicle configured to replace the one or more chemical containers in the ejected holder.Type: ApplicationFiled: December 19, 2018Publication date: April 2, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu Kai CHEN, Forster Yuan, Ko-BIn Kao, Shi-Ming Wang, Su-Yu Yeh, Li-Jen Wu, Oliver Yu
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Publication number: 20200043762Abstract: The present disclosure describes a container for placing an object therein. The container includes a container body and a lid over the container body, a collision-preventing portion attached to one or more of the container body and the lid and configured to buffer an impact force, a pairing recognition mechanism configured to detect an object placed in the container body, and a liquid-detecting sensor configured to detect a leakage from the object.Type: ApplicationFiled: December 27, 2018Publication date: February 6, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu Kai CHEN, Chia-Hung CHUNG, Ko-Bin KAO, Shi-Ming WANG, Su-Yu YEH, Li-Jen WU, Oliver YU, Wen-Shiung CHEN
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Publication number: 20190157124Abstract: A method for monitoring gas in a wafer processing system is provided. The method includes producing an exhaust flow in an exhausting conduit from a processing chamber. The method further includes placing a gas sensor in fluid communication with a detection point located in the exhausting conduit via a sampling tube that passes through a through hole formed on the exhausting conduit. The detection point is located away from the through hole. The method also includes detecting a gas condition at the detection point with the gas sensor. In addition, the method also includes analyzing the gas condition detected by the gas sensor to determine if the gas condition in the exhausting conduit is in a range of values.Type: ApplicationFiled: September 11, 2018Publication date: May 23, 2019Inventors: Wen-Chieh HSIEH, Su-Yu YEH, Ko-Bin KAO, Chia-Hung CHUNG, Li-Jen WU, Chun-Yu CHEN, Hung-Ming CHEN, Yong-Ting WU
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Publication number: 20190146348Abstract: A method of manufacturing a semiconductor device and a semiconductor processing system are provided. The method includes the following steps. A photoresist layer is formed on a substrate in a lithography tool. The photoresist layer is exposed in the lithography tool to form an exposed photoresist layer. The exposed photoresist layer is developed to form a patterned photoresist layer in the lithography tool by using a developer. An ammonia gas by-product of the developer is removed from the lithography tool.Type: ApplicationFiled: February 26, 2018Publication date: May 16, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Kai Chen, Chia-Hung Chung, Ko-Bin Kao, Su-Yu Yeh, Li-Jen Wu, Zhi-You Ke, Ming-Hung Lin
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Publication number: 20190148333Abstract: A method is provided and includes the following steps. A first wafer is coupled to a first support of a bonding tool and a second wafer is coupled to a second support of the bonding tool. The second wafer is bonded to the first wafer with the first wafer coupled to the first support. Whether a bubble is between the bonded first and second wafers in the bonding tool is detected.Type: ApplicationFiled: January 12, 2018Publication date: May 16, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Chih CHEN, Tsung-Yi YANG, Chung-I HUNG, Mu-Han CHENG, Tzu-Shin CHEN, Su-Yu YEH
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Patent number: 10050159Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided. In the method for fabricating the semiconductor device, at first, a dielectric layer is provided. Then, trenches are formed in the dielectric layer. Thereafter, the trenches are filled with spacer material to form a spacer structure in the dielectric layer for defining pixel regions. Then, lens structures are formed on the pixel regions. Each of the lens structures includes a first curved lens layer, a second curved lens layer and a curved color filter layer. The curved color filter layer is disposed on the second curved lens layer or between the first curved lens layer and the second curved lens layer.Type: GrantFiled: December 12, 2016Date of Patent: August 14, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Chih Chen, Su-Yu Yeh, Tzu-Shin Chen, Mu-Han Cheng, Chun-Hai Huang
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Publication number: 20180166594Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided. In the method for fabricating the semiconductor device, at first, a dielectric layer is provided. Then, trenches are formed in the dielectric layer. Thereafter, the trenches are filled with spacer material to form a spacer structure in the dielectric layer for defining pixel regions. Then, lens structures are formed on the pixel regions. Each of the lens structures includes a first curved lens layer, a second curved lens layer and a curved color filter layer. The curved color filter layer is disposed on the second curved lens layer or between the first curved lens layer and the second curved lens layer.Type: ApplicationFiled: December 12, 2016Publication date: June 14, 2018Inventors: Chien-Chih Chen, Su-Yu Yeh, Tzu-Shin Chen, Mu-Han Cheng, Chun-Hai Huang
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Patent number: 6875705Abstract: A method for forming salicides with lower sheet resistance and increased sheet resistance uniformity over a semiconductor process wafer including providing a semiconductor process wafer having exposed silicon containing areas at a process surface; depositing a metal layer including at least one of cobalt and titanium over the process surface; carrying out at least one thermal annealing process to react the metal layer and silicon to form a metal silicide over the silicon containing areas; and, wet etching unsilicided areas of the metal layer with a wet etching solution including phosphoric acid (H3PO4), nitric acid (HNO3), and a carboxylic acid to leave salicides covering silicon containing areas at the process surface.Type: GrantFiled: September 4, 2002Date of Patent: April 5, 2005Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Jie Tsai, Jeng Yang Pan, Chin-Nan Wu, Meng-Chang Liu, Su-Yu Yeh
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Patent number: 6702900Abstract: A wafer chuck for use in a semiconductor process chamber capable of producing an inert gas blanket positioned on the chuck from residual chemical vapor in the chamber is disclosed. A plurality of mounting pins for supporting a wafer is further provided in the upper surface for forming an inert gas into a cavity formed between the wafer and the upper surface of the chuck. A plurality of apertures in a sidewall of the body portion for flowing an inert gas into the lower chamber forming an inert gas blanket blocking a passageway between the upper and lower chambers, thus preventing the wafer from damage by residual chemical vapor in the lower chamber.Type: GrantFiled: March 22, 2001Date of Patent: March 9, 2004Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Su-Yu Yeh, Huai-Tei Yang, Cheng-Yang Pan, Jun-Yang Lai
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Publication number: 20040043624Abstract: A method for forming salicides with lower sheet resistance and increased sheet resistance uniformity over a semiconductor process wafer including providing a semiconductor process wafer having exposed silicon containing areas at a process surface; depositing a metal layer including at least one of cobalt and titanium over the process surface; carrying out at least one thermal annealing process to react the metal layer and silicon to form a metal silicide over the silicon containing areas; and, wet etching unsilicided areas of the metal layer with a wet etching solution including phosphoric acid (H3PO4), nitric acid (HNO3), and a carboxylic acid to leave salicides covering silicon containing areas at the process surface.Type: ApplicationFiled: September 4, 2002Publication date: March 4, 2004Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Jie Tsai, Jeng Yang Pan, Chin-Nan Wu, Meng-Chang Liu, Su-Yu Yeh