Patents by Inventor Su-Yu Yeh

Su-Yu Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030160179
    Abstract: A method for reducing a dinitrogen (N2) ion concentration in an ion implanter including providing an ion implanter having an ion source chamber for producing source ions said ion source chamber surrounded by a plurality of source magnets having a current supply for altering a position of said source ions; providing a gaseous source of material to the ion source chamber for ionization thereby creating a supply of source ions for implantation; creating a supply of source ions to include dinitrogen (N2) ions and nitrogen (N) ions supplied for implantation; and, increasing a current supply to at least one of the plurality of source magnets such that a ratio of dinitrogen (N2) ions to nitrogen (N) ions supplied for implantation is reduced.
    Type: Application
    Filed: February 22, 2002
    Publication date: August 28, 2003
    Applicant: Taiwn Semiconductor Manufacturing Co., Ltd.
    Inventors: Su-Yu Yeh, Chi-Bing Chen, Cheng-Yi Huang, Chao-Jie Tsai, Lu-Chang Chen, Hsing-Jui Lee
  • Patent number: 6605812
    Abstract: A method for reducing a dinitrogen (N2) ion concentration in an ion implanter including providing an ion implanter having an ion source chamber for producing source ions said ion source chamber surrounded by a plurality of source magnets having a current supply for altering a position of said source ions; providing a gaseous source of material to the ion source chamber for ionization thereby creating a supply of source ions for implantation; creating a supply of source ions to include dinitrogen (N2) ions and nitrogen (N) ions supplied for implantation; and, increasing a current supply to at least one of the plurality of source magnets such that a ratio of dinitrogen (N2) ions to nitrogen (N) ions supplied for implantation is reduced.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: August 12, 2003
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Su-Yu Yeh, Chi-Bing Chen, Cheng-Yi Huang, Chao-Jie Tsai, Lu-Chang Chen, Hsing-Jui Lee
  • Patent number: 6530103
    Abstract: A method for eliminating wafer breakage during a wafer transfer process in a grinding apparatus by a wafer transfer pad and an apparatus for conducting such method are disclosed. In the method, a surface of the vacuum pad, or the wafer transfer pad, that is formed of sintered ceramic is first cleaned by contacting a rotating brush and a spray of cleaning solvent. The invention further discloses an apparatus for eliminating wafer breakage during the wafer transfer process by a vacuum pad by incorporating a pressure regulating valve situated in the vacuum conduit such that a vacuum pressure applied can be regulated at a rate not higher than 30 psi/sec. to the surface of the wafer transfer pad.
    Type: Grant
    Filed: June 21, 2001
    Date of Patent: March 11, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Yang Pan, Chia-Chun Wu, Wen-Fang Tang, Su-Yu Yeh, Huai-Tei Yang
  • Publication number: 20020194689
    Abstract: A method for eliminating wafer breakage during a wafer transfer process in a grinding apparatus by a wafer transfer pad and an apparatus for conducting such method are disclosed. In the method, a surface of the vacuum pad, or the wafer transfer pad, that is formed of sintered ceramic is first cleaned by contacting a rotating brush and a spray of cleaning solvent. The invention further discloses an apparatus for eliminating wafer breakage during the wafer transfer process by a vacuum pad by incorporating a pressure regulating valve situated in the vacuum conduit such that a vacuum pressure applied can be regulated at a rate not higher than 30 psi/sec. to the surface of the wafer transfer pad.
    Type: Application
    Filed: June 21, 2001
    Publication date: December 26, 2002
    Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.
    Inventors: Jeng-Yang Pan, Chia-Chun WU, Wen-Fang Tang, Su-Yu Yeh, Huai-Tei Yang
  • Publication number: 20020134514
    Abstract: A wafer chuck for use in a semiconductor process chamber capable of producing an inert gas blanket positioned on the chuck from residual chemical vapor in the chamber is disclosed. A plurality of mounting pins for supporting a wafer is further provided in the upper surface for forming an inert gas into a cavity formed between the wafer and the upper surface of the chuck. A plurality of apertures in a sidewall of the body portion for flowing an inert gas into the lower chamber forming an inert gas blanket blocking a passageway between the upper and lower chambers, thus preventing the wafer from damage by residual chemical vapor in the lower chamber.
    Type: Application
    Filed: March 22, 2001
    Publication date: September 26, 2002
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Su-Yu Yeh, Huai-Tei Yang, Cheng-Yang Pan, Jun-Yang Lai
  • Patent number: 6444541
    Abstract: A method for forming lining oxide in an opening for a shallow trench isolation and a method for forming a shallow trench isolation incorporating a lining oxide layer are described. In the method for forming lining oxide, a silicon substrate is first provided, followed by a process of forming a pad oxide layer and a silicon nitride mask sequentially on top of the silicon substrate. A trench opening is then patterned and formed in the silicon substrate for the shallow trench isolation. The silicon substrate is then annealed at a temperature of at least 1,000° C. in a furnace in an environment that contains not more than 10 vol. % oxygen. A lining oxide layer is formed in the same furnace used for annealing the structure of the trench opening in the silicon substrate.
    Type: Grant
    Filed: August 14, 2000
    Date of Patent: September 3, 2002
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Jun-Yang Lai, Jih-Hwa Wang, Chou-Jie Tsai, Chin-Te Huang, Su-Yu Yeh, Meng-Shiun Shieh, Jang-Cheng Hsieh, Chung-Te Lin
  • Patent number: 6372663
    Abstract: A method for forming silicon oxide layers on silicon wafers by a wet oxidation process that utilizes a dual-stage pyrolysis is described. The process can be carried out by flowing a first H2/O2 mixture that has a first H2/O2 gas mixture ratio into a torch and then feeding water vapor generated into the wet oxidation chamber to form a first layer of silicon oxide, and then flowing a second H2/O2 mixture that has a second H2/O2 gas mixture ratio into the torch and feeding water vapor generated into the wet oxidation chamber for forming a second thickness of the silicon oxide layer. The second H2/O2 ratio is smaller than the first H2/O2 ratio by at least ⅓ of the value of the first H2/O2 ratio. For instance, when the first H2/O2 ratio used is large than 1.5, the second H2/O2 ratio used is less than 1.2. In one example, the first H2/O2 gas mixture ratio utilized is 1.8, while the second H2/O2 gas mixture ratio utilized is 1.0. It has been found that by reducing the hydrogen content, i.e.
    Type: Grant
    Filed: January 13, 2000
    Date of Patent: April 16, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Su-Yu Yeh, Chien-Jiun Wang, Jih-Hwa Wang