Abstract: An integrated circuit includes a first standard cell including a first first-type transistor, a first second-type transistor, a third second-type transistor, and a third first-type transistor, a second standard cell including a second first-type transistor, a second second-type transistor, a fourth second-type transistor and a fourth first-type transistor, a plurality of wiring layers which are disposed on the first and second standard cells and includes a first wiring layer, a second wiring layer, and a third wiring layer sequentially stacked. A source contact of the first first-type transistor and a source contact of the second first-type transistor are electrically connected through a first power rail of the plurality of wiring layers, and a source contact of the third first-type transistor and a source contact of the fourth first-type transistor are electrically connected through a second power rail of the plurality of wiring layers.

Abstract: An AI motion recognition based smart hometraining platform is configured to include: a photographing unit; an motion image generation unit; a joint information generation unit; a deep learning determination unit determining whether the user motion is suitable by inputting user joint information; a correction information generation unit extracting correction information, and generating an image for a correction image or correction information based on the extracted correction information; a user image generation unit generating a user image acquired by overlaying a joint information image of the joint information generation unit to the user image; and a display displaying both the image for the correction message or the correction information and the user image of the user image generation unit in the display.

Abstract: A semiconductor device includes a first and second active pattern extending in a first direction on a substrate, a first and second gate electrode extending in a second direction to intersect the first and second active pattern, a first source/drain contact extending in the second direction and connected to a first and source/drain region of the first and second active patterns, respectively, a first source/drain via connected to the first source/drain contact, a first cell separation film extending in the second direction and crosses the first active pattern and the second active pattern, between the first source/drain contact and the second gate electrode, a first gate via connected to the second gate electrode and arranged with the first source/drain via along the first direction, and a first connection wiring which extending in the first direction and connects the first source/drain via and the first gate via.

Abstract: A method of manufacturing a semiconductor device is as below. An exposed photoresist layer is developed using a developer supplied by a developer supplying unit. An ammonia gas by-product of the developer is discharged through a gas outlet of the developer supplying unit into a treating tool. The ammonia gas by-product is retained in the treating tool. A concentration of the ammonia gas by-product is monitored.

Abstract: An image sensor includes a substrate, a grid, and a color filter. The grid is over the substrate. From a cross-sectional view, the grid includes a first grid and a second grid over the first grid, the first grid has lower portion that has a first sidewall and a second sidewall opposing the first sidewall, the second grid has a third sidewall and a fourth sidewall opposing the third sidewall, and a width between the third sidewall and the fourth sidewall is less than a width between the first sidewall and the second sidewall. The color filter extends through the grid structure.

Abstract: The present invention relates to a perovskite solar cell module and a manufacturing method for same. The perovskite solar cell module comprises a plurality of perovskite solar cells disposed on a substrate, each of the perovskite solar cells comprising: a first electrode, a first charge transport layer on the first electrode, an optical active layer formed of a perovskite crystal structure, and a second charge transport layer, which are laminated in this order; and a second electrode laminated on the second charge transport layer, wherein the second electrode included in each of the cells can be electrically connected in series to the first electrode of the closest perovskite solar cell and enhance the photoelectric conversion efficiency of the perovskite solar cell module.

Abstract: A catalyst for preparing a synthesis gas includes: a mesoporous Al2O3 support including mesopores having a pore size of about 1 nm to about 30 nm; metal nanoparticles supported in the mesopores of the mesoporous Al2O3 support wherein the metal nanoparticles have a particle size of less than or equal to about 20 nm; and a metal oxide coating layer including particles wherein the metal oxide coating layer is coated on the surface of the mesoporous Al2O3 support and includes mesopores having a pore size of about 2 nm to about 50 nm.

Abstract: Disclosed is a method for preparing a synthesis gas. The method may include performing a combined reforming reaction by injecting a reaction gas including water (H2O) and heat-treating it in the presence of the catalyst. The catalyst may include a mesoporous support including regularly distributed mesopores, metal nanoparticles supported on the support, and a metal oxide coating layer coated on a surface of the support.

Abstract: The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot; performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.

Abstract: The present disclosure relates to a ternary catalyst coated with a metal oxide, the ternary catalyst including: a ternary catalyst core including a hydrotalcite support and metal particles dispersed on the support; and a metal oxide shell formed on the ternary catalyst core.

Abstract: A method includes sequentially depositing a floating gate layer, a dielectric structure stack, and a control gate layer over a substrate. A first etching process is performed to pattern the control gate layer, the dielectric structure stack, and a top portion of the floating gate layer to form a control gate, a dielectric structure, and a top portion of a floating gate over a bottom portion of the floating gate layer. A sidewall of the top portion of the floating gate is concave. A first spacer structure is formed on the sidewall of the top portion of the floating gate, a sidewall of the dielectric structure, and a sidewall of the control gate. A second etching process is performed to pattern the bottom portion of the floating gate layer to form a bottom portion of the floating gate after forming the first spacer structure.

Abstract: An integrated circuit includes a first standard cell including a first p-type transistor, a first n-type transistor, a first gate stack intersecting first and second active regions, first extended source/drain contacts on a first side of the first gate stack, a first normal source/drain contact on a second side of the first gate stack, a first gate via connected to the first gate stack, and a first source/drain via connected to the first normal source/drain contact, a second standard cell adjacent the first standard cell and including a second p-type transistor, a second n-type transistor, a second gate stack intersecting the first and second active regions, and a second gate via connected to the second gate stack, an input wiring connected to the first gate via, and an output wiring at a same level as the input wiring to connect the first source/drain via and the second gate via.

Abstract: A method includes depositing a gate dielectric film over a substrate. A floating gate layer and a control gate layer are deposited over the gate dielectric film. The control gate layer is patterned to form a control gate over the floating gate layer. A top portion of the floating gate layer is patterned. A spacer structure is formed on a sidewall of the control gate and over a remaining portion of the floating gate layer. The remaining portion of the floating gate layer is patterned to form a bottom portion of a floating gate. A ratio of the bottom width of the bottom portion to the middle width of the bottom portion is in a range between about 103% and about 108%. The gate dielectric film is patterned form a gate dielectric layer.

Abstract: According to some embodiments of the present disclosure, a semiconductor device includes a first power rail configured to provide a first voltage and extending in a first direction, a substrate comprising a first well having a first conductivity type and a second well having a second conductivity type, a first well tap having the first conductivity type, on the first well; a first source/drain region having the second conductivity type, on the first well; a first source/drain contact extending in a second direction and electrically connected to the first power rail, on the first source/drain region, a first connection wiring electrically connected to the first source/drain contact and extending in the first direction, and a first well contact electrically connected to the first connection wiring, on the first well tap.

Abstract: An integrated circuit including a plurality of standard cells is provided. The integrated circuit includes a first standard cell group including at least two first standard cells, a second standard cell group adjacent to the first standard cell group in a first direction, the second standard cell group including at least one second standard cell, and a first insulating gate bordered by one side of at least one of the first standard cells and one side of the at least one second standard cell, wherein each of the first and second standard cells includes a p-type transistor (pFET) and an n-type transistor (nFET) which are integrated, wherein each of the first and second standard cells has first wiring lines of different designs, and wherein each of the first and second standard cells has the same or different placement of an active region according to the corresponding design.

Abstract: Disclosed are a catalyst for preparing a synthetic gas through dry reforming, a method preparing the catalyst, and a method using the catalyst for preparing the synthetic gas. The catalyst may include: a support including regularly distributed mesopores; metal nanoparticles supported on the support; and a metal oxide coating layer coated on a surface of the support.

Abstract: In a method for forming a semiconductor device photo-sensing regions are formed over a frontside of a substrate. A first layer is formed over a backside of the substrate and is patterned to form a plurality of grid lines. The grid lines can define a plurality of first areas and a plurality of second areas. A second layer may be formed over exposed portions of the backside, the gridlines, the first areas, and the second areas and a third layer may be formed over the second layer. The second and third layer may have different etch rates and the third layer is pattern so as to remove the third layer from over the plurality of first areas.

Abstract: A method incudes forming a plurality of photodiodes in a substrate; forming an interconnect structure on a front-side of the substrate; forming a barrier layer on a back-side of the substrate; depositing a metal layer over the barrier layer; forming an adhesion enhancement layer over the metal layer; forming an oxide layer over the adhesion enhancement layer; etching the oxide layer, the adhesion enhancement layer, the metal layer, and the barrier layer to form an oxide grid, an adhesion enhancement grid, a metal grid, and a barrier grid, respectively, wherein the barrier grid and the adhesion enhancement grid have a same chemical element.

Abstract: A catalyst for preparing a synthesis gas includes: a mesoporous Al2O3 support including mesopores having a pore size of about 1 nm to about 30 nm; metal nanoparticles supported in the mesopores of the mesoporous Al2O3 support wherein the metal nanoparticles have a particle size of less than or equal to about 20 nm; and a metal oxide coating layer including particles wherein the metal oxide coating layer is coated on the surface of the mesoporous Al2O3 support and includes mesopores having a pore size of about 2 nm to about 50 nm.

Abstract: A system and method for cleaning a preclean process chamber in between wafer processing. The internal pressure of the preclean process chamber is reduced to a first pressure and a first gas that consists of oxygen and an inert or noble gas, is introduced into the chamber. Plasma is generated within the preclean process chamber using the first gas at the first pressure. Internal pressure is then reduced to a second pressure, less than the first, and the first gas is continued into the chamber. Plasma is then generated using the first gas at the second pressure. Thereafter, a second gas, consisting of an oxygen-free inert or noble gas, is introduced into the chamber at the second pressure, following which plasma is generated within the chamber using only the second gas.