Patents by Inventor Su Yu

Su Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210165947
    Abstract: A layout method is provided. The layout method may include placing first and second standard cells from a standard cell library, interconnecting the placed standard cells to generate a layout draft, confirming placement and routing at a boundary region between the interconnected standard cells, and revising the layout draft based on the confirmation. Each of the standard cells includes, in part, a conductive line that extends in the first direction and is interconnected to an adjacent standard cell through a source/drain via. To confirm the placement and routing, a first spaced distance from a tip of one of the conductive lines to a tip of the other conductive line, and a second spaced distance from the tip of the first conductive line to the cell boundary are compared with preset threshold values. Revising the layout draft may include adjusting a tip position of one of the conductive lines.
    Type: Application
    Filed: November 3, 2020
    Publication date: June 3, 2021
    Inventors: JAE-HO PARK, SANGHOON BAEK, JI SU YU, HYEON GYU YOU, SEUNG YOUNG LEE, SEUNG MAN LIM, MIN JAE JEONG, JONG HOON JUNG
  • Patent number: 11017598
    Abstract: An image processing apparatus is disclosed. The image processing apparatus comprises: a receiver configured to receive an input frame including a plurality of image regions, corresponding to a plurality of faces of a three-dimensional polyhedron, and metadata; and a processor configured to render an output frame including at least one a part of the input frame, on the basis of padding information included in the metadata. Here, the processor may be configured to identify, on the basis of the padding information, a padding region included in at least one of the plurality of image regions, and render, on the basis of the determined padding region, a boundary between at least one face of the plurality of faces and another face of the plurality of faces adjoining the at least one face of the polyhedron.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: May 25, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Po Choi, In-Su Yu, Jin-Ho Lim, Il-Hoe Jung, David Bernardino Martins Sena, Frederic Garnier, Yoon-Joo Kim, Jung-Eun Lee
  • Publication number: 20210137945
    Abstract: Provided herein is a method for the treatment and/or prophylaxis of a cancer associated with galectin-1. The method includes administering to a subject a pharmaceutical composition that mainly composed of ganoderic acid S (GAS) and ganoderic acid T (GAT). The method further includes administering to the subject another anti-cancer agent before, together with, or after the administration of the present pharmaceutical composition, so as to synergistically suppress the growth of the cancer.
    Type: Application
    Filed: November 13, 2019
    Publication date: May 13, 2021
    Applicant: TRINEO BIOTECHNOLOGY CO. LTD
    Inventors: Teng-Hai CHEN, Mon-Tarng CHEN, Chien-Yuan WANG, Cheng-Po HUANG, Su-Yu CHEN, Yi-Hsiu LIN, Ssu-Chia WANG, Chih-Yuan LIAO
  • Patent number: 11004709
    Abstract: A method for monitoring gas in a wafer processing system is provided. The method includes producing an exhaust flow in an exhausting conduit from a processing chamber. The method further includes placing a gas sensor in fluid communication with a detection point located in the exhausting conduit via a sampling tube that passes through a through hole formed on the exhausting conduit. The detection point is located away from the through hole. The method also includes detecting a gas condition at the detection point with the gas sensor. In addition, the method also includes analyzing the gas condition detected by the gas sensor to determine if the gas condition in the exhausting conduit is in a range of values.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: May 11, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Chieh Hsieh, Su-Yu Yeh, Ko-Bin Kao, Chia-Hung Chung, Li-Jen Wu, Chun-Yu Chen, Hung-Ming Chen, Yong-Ting Wu
  • Publication number: 20210134837
    Abstract: An integrated circuit includes a first standard cell including a first first-type transistor, a first second-type transistor, a third second-type transistor, and a third first-type transistor, a second standard cell including a second first-type transistor, a second second-type transistor, a fourth second-type transistor and a fourth first-type transistor, a plurality of wiring layers which are disposed on the first and second standard cells and includes a first wiring layer, a second wiring layer, and a third wiring layer sequentially stacked. A source contact of the first first-type transistor and a source contact of the second first-type transistor are electrically connected through a first power rail of the plurality of wiring layers, and a source contact of the third first-type transistor and a source contact of the fourth first-type transistor are electrically connected through a second power rail of the plurality of wiring layers.
    Type: Application
    Filed: May 30, 2020
    Publication date: May 6, 2021
    Inventors: Hyeon Gyu YOU, In Gyum KIM, Gi Young YANG, Ji Su YU, Jin Young LIM, Hak Chul JUNG
  • Publication number: 20210104611
    Abstract: A semiconductor device includes a first and second active pattern extending in a first direction on a substrate, a first and second gate electrode extending in a second direction to intersect the first and second active pattern, a first source/drain contact extending in the second direction and connected to a first and source/drain region of the first and second active patterns, respectively, a first source/drain via connected to the first source/drain contact, a first cell separation film extending in the second direction and crosses the first active pattern and the second active pattern, between the first source/drain contact and the second gate electrode, a first gate via connected to the second gate electrode and arranged with the first source/drain via along the first direction, and a first connection wiring which extending in the first direction and connects the first source/drain via and the first gate via.
    Type: Application
    Filed: April 24, 2020
    Publication date: April 8, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ji Su YU, Hyeon Gyu YOU, Seung Man LIM
  • Patent number: 10943802
    Abstract: The present disclosure describes a container for placing an object therein. The container includes a container body and a lid over the container body, a collision-preventing portion attached to one or more of the container body and the lid and configured to buffer an impact force, a pairing recognition mechanism configured to detect an object placed in the container body, and a liquid-detecting sensor configured to detect a leakage from the object.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu Kai Chen, Chia-Hung Chung, Ko-Bin Kao, Shi-Ming Wang, Su-Yu Yeh, Li-Jen Wu, Oliver Yu, Wen-Shiung Chen
  • Patent number: 10928247
    Abstract: A system for detecting an illuminance of the present invention includes a light source, a light sensor, and a signal output module. The light source includes a first A light-emitting diode, the first A light-emitting diode having a first color light; and the light source emits a first ray of light. The light sensor has a sensing face; the light sensor includes a first B light-emitting diode disposed on the sensing face, the first B light-emitting diode having the first color light; and the light sensor receives at least a portion of the first ray of light and generates a first sensing voltage. The signal output module is coupled to the light sensor to receive the first sensing voltage and output a sensing result signal according to the first sensing voltage.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: February 23, 2021
    Assignee: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Fang-Ci Su, Hsin-Yi Tsai, Min-Wei Hung, Yi-Cheng Lin, Kuo-Cheng Huang, Hsin-Su Yu, Chiou-Lian Lai, Chung-Yao Hsu, Chao-Hung Cheng, Li-Wei Kuo
  • Patent number: 10912948
    Abstract: The present invention provides a composite intelligent biological phototherapy device including a base structure, a plurality of white light fluorescent tubes arranged side by side on the base structure, a plurality of LEDs disposed between the white light fluorescent tubes, a housing having an opening and configured to accommodate the base structure and the white light fluorescent tubes and the LEDs thereon, a light-transmittable plate disposed on the housing corresponding to the opening, and an control module configured to respectively control the white light fluorescent tubes and the LEDs. The base structure includes a plurality of sections, and each of the sections has a first surface facing the light-transmittable plate. The white light fluorescent tubes and the LEDs are provided on the first surfaces, and the sections are bent relative to each other so an angle between the first surfaces of adjacent sections is less than 180 degrees.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: February 9, 2021
    Assignee: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Yi-Cheng Lin, Hsin-Yi Tsai, Min-Wei Hung, Kuo-Cheng Huang, Hsin-Su Yu, Chiou-Lian Lai, Chung-Yao Hsu, Chao-Hung Cheng, Li-Wei Kuo, Hung-Che Chiang, Chih-Yi Yang
  • Publication number: 20210036179
    Abstract: A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.
    Type: Application
    Filed: May 4, 2020
    Publication date: February 4, 2021
    Inventors: Chih Wei Sung, Chung-Bin Tseng, Keng-Ying Liao, Yen-Jou Wu, Po-Zen Chen, Su-Yu Yeh, Ching-Chung Su
  • Publication number: 20210036118
    Abstract: A memory device includes a floating gate, a control gate, a spacer structure, a dielectric layer, and an erase gate. The floating gate is above a substrate. The floating gate has a curved sidewall. The control gate is above the floating gate. The spacer structure is in contact with the control gate and the floating gate. The spacer structure is spaced apart from the curved sidewall of the floating gate. The dielectric layer is in contact with the spacer structure and the curved sidewall of the floating gate. The erase gate is above the dielectric layer.
    Type: Application
    Filed: May 20, 2020
    Publication date: February 4, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chu LIN, Chi-Chung JEN, Chia-Ming PAN, Su-Yu YEH, Keng-Ying LIAO, Chih-Wei SUNG
  • Publication number: 20210020669
    Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a metal catalyst layer on an etching area of the semiconductor substrate; performing a wet etch process to the semiconductor substrate to etch the etching area of the semiconductor substrate under the metal catalyst layer, thereby forming a trench in the semiconductor substrate; and removing the metal catalyst layer from the semiconductor substrate after performing the wet etch process.
    Type: Application
    Filed: July 15, 2019
    Publication date: January 21, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Yu LIN, Keng-Ying LIAO, Huai-Jen TUNG, Po-Zen CHEN, Su-Yu YEH, Chia-Yun CHEN, Ta-Cheng WEI
  • Publication number: 20210013149
    Abstract: An integrated circuit including: a power rail including first and second conductive lines spaced apart from each other in a vertical direction, wherein the first and second conductive lines extend in parallel to each other in a first horizontal direction, and are electrically connected to each other, to supply power to a first standard cell, wherein the first and second conductive lines are disposed at a boundary of the first standard cell; and a third conductive line between the first and second conductive lines and extending in a second horizontal direction orthogonal to the first horizontal direction, to transfer an input signal or an output signal of the first standard cell.
    Type: Application
    Filed: September 29, 2020
    Publication date: January 14, 2021
    Inventors: Jae-Boong Lee, Jung-Ho Do, Tae-Joong Song, Seung-Young Lee, Jong-Hoon Jung, Ji-Su Yu
  • Publication number: 20210013230
    Abstract: An integrated circuit includes a standard cell. The standard cell may include a plurality of gate lines and a plurality of first wirings. The plurality of first wirings may include a clubfoot structure conductive pattern that includes a first conductive pattern and a second conductive pattern spaced apart from each other. Each of the first conductive pattern and the second conductive pattern may include a first line pattern extending in a first direction and a second line pattern protruding from one end of the first line pattern in a direction perpendicular to the first direction. The plurality of gate lines may be spaced apart from each other by a first pitch in the first direction, and the plurality of second wirings may be spaced apart from each other by a second pitch in the first direction. The first pitch may be greater than the second pitch.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jung-ho DO, Ji-Su YU, Hyeon-gyu YOU, Seung-Young LEE, Jae-boong LEE, Jong-hoon JUNG
  • Patent number: 10879289
    Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a metal catalyst layer on an etching area of the semiconductor substrate; performing a wet etch process to the semiconductor substrate to etch the etching area of the semiconductor substrate under the metal catalyst layer, thereby forming a trench in the semiconductor substrate; and removing the metal catalyst layer from the semiconductor substrate after performing the wet etch process.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Yu Lin, Keng-Ying Liao, Huai-Jen Tung, Po-Zen Chen, Su-Yu Yeh, Chia-Yun Chen, Ta-Cheng Wei
  • Patent number: 10872873
    Abstract: A method is provided and includes the following steps. A first wafer is coupled to a first support of a bonding tool and a second wafer is coupled to a second support of the bonding tool. The second wafer is bonded to the first wafer with the first wafer coupled to the first support. Whether a bubble is between the bonded first and second wafers in the bonding tool is detected.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Chih Chen, Tsung-Yi Yang, Chung-I Hung, Mu-Han Cheng, Tzu-Shin Chen, Su-Yu Yeh
  • Publication number: 20200388002
    Abstract: An image processing apparatus is disclosed. The image processing apparatus includes a storage unit; a transceiver; and a processor for controlling the storage unit to store an input frame including a plurality of image areas having preset arrangement attributes and metadata including the preset arrangement attributes, control the transceiver to receive viewing angle information, and control the transceiver to transmit the metadata and image data of at least one image region corresponding to the viewing angle information among the plurality of image regions by using at least one of the plurality of transmission channels matched with the plurality of image regions.
    Type: Application
    Filed: November 27, 2017
    Publication date: December 10, 2020
    Inventors: Il-Hoe JUNG, In-Su YU, Jin-Ho LIM, Byung-Po CHOI, Yoon-Joo KIM, Byung-Hyun AHN, Jae-Eun YANG, Dong-Hyun YEOM
  • Publication number: 20200373344
    Abstract: The present disclosure describes the formation of a pad structure in an image sensor device using a sacrificial isolation region and a silicon oxide based stack with no intervening nitride etch-stop layers. The image sensor device includes a semiconductor layer comprising a first horizontal surface opposite to a second horizontal surface; a metallization layer formed on the second horizontal surface of the semiconductor layer, where the metallization layer includes a dielectric layer. The image sensor device also includes a pad region traversing through the semiconductor layer from the first horizontal surface to the second horizontal surface. The pad region includes an oxide layer with no intervening nitride layers formed on the dielectric layer of the metallization layer and a pad structure in physical contact with a conductive structure of the metallization layer.
    Type: Application
    Filed: May 24, 2019
    Publication date: November 26, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huai-jen TUNG, Ching-Chung SU, Keng-Ying LIAO, Po-Zen CHEN, Su-Yu YEH, S.Y. CHEN
  • Patent number: 10811357
    Abstract: An integrated circuit including: a power rail including first and second conductive lines spaced apart from each other in a vertical direction, wherein the first and second conductive lines extend in parallel to each other in a first horizontal direction, and are electrically connected to each other, to supply power to a first standard cell, wherein the first and second conductive lines are disposed at a boundary of the first standard cell; and a third conductive line between the first and second conductive lines and extending in a second horizontal direction orthogonal to the first horizontal direction, to transfer an input signal or an output signal of the first standard cell.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: October 20, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Boong Lee, Jung-Ho Do, Tae-Joong Song, Seung-Young Lee, Jong-Hoon Jung, Ji-Su Yu
  • Patent number: 10790305
    Abstract: An integrated circuit includes a standard cell. The standard cell may include a plurality of gate lines and a plurality of first wirings. The plurality of first wirings may include a clubfoot structure conductive pattern that includes a first conductive pattern and a second conductive pattern spaced apart from each other. Each of the first conductive pattern and the second conductive pattern may include a first line pattern extending in a first direction and a second line pattern protruding from one end of the first line pattern in a direction perpendicular to the first direction. The plurality of gate lines may be spaced apart from each other by a first pitch in the first direction, and the plurality of second wirings may be spaced apart from each other by a second pitch in the first direction. The first pitch may be greater than the second pitch.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: September 29, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-ho Do, Ji-Su Yu, Hyeon-gyu You, Seung-Young Lee, Jae-Boong Lee, Jong-Hoon Jung