Abstract: Embodiments of the present disclosure describe techniques for providing an apparatus with a substrate provided with plasma treatment. In some instances, the apparatus may include a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus. The metal layer may be provided in response to a plasma treatment of the surface with a functional group containing a gas (e.g., nitrogen-based gas), to provide absorption of a transition metal catalyst into the surface, and subsequent electroless plating of the surface with a metal. The transition metal catalyst is to enhance electroless plating of the surface with the metal. Other embodiments may be described and/or claimed.

Abstract: Conductive routes for an electronic substrate may be fabricated by forming an opening in a material, using existing laser drilling or lithography tools and materials, followed by selectively plating a metal on the sidewalls of the opening. The processes of the present description may result in significantly higher patterning resolution or feature scaling (up to 2× improvement in patterning density/resolution). In addition to improved patterning resolution, the embodiments of the present description may also result in higher aspect ratios of the conductive routes, which can result in improved signaling, reduced latency, and improved yield.

Abstract: The present disclosure provides a substrate for an integrated circuit. The substrate includes a dielectric layer. The substrate further includes a plurality of conductive elements at least partially embedded within the dielectric layer and having a substantially smooth outer surface. The substrate further includes an interlayer disposed between the individual conductive elements and the dielectric layer. The interlayer has a first surface comprising a plurality of protrusions interlocked with the dielectric layer and a second surface adhered to the outer surface of the individual conductive elements.

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

Abstract: Techniques and mechanisms for bonding structures of a circuit device with a monolayer. In an embodiment, a patterned metallization layer or a first dielectric layer includes a first surface portion. The first surface portion is exposed to first molecules which each include a first head group and a first end group which is substantially non-reactive with the first head group. The first head groups attach to the first portion to form a first self-assembled monolayer, which is subsequently reacted with second molecules to form a second monolayer comprising moieties of the first molecules. In another embodiment, the first head group comprises a first moiety comprising a sulfur atom or a nitrogen atom, where the first end group comprises one of an acid moiety, an acid anhydride moiety, an aliphatic alcohol moiety, an aromatic alcohol moiety, or an unsaturated hydrocarbon moiety.

Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a self-assembled monolayers (SAM) layer. The package substrate includes a SAM layer on portions of a conductive pad, where the SAM layer includes light-reflective moieties. The package substrate also includes a via on a surface portion of the conductive pad, and a dielectric on and around the via, the SAM layer, and the conductive pad, where the SAM layer surrounds and contacts a surface of the via. The SAM layer may be an interfacial organic layer. The light-reflective moieties may include a hemicyanine, a cyclic-hemicyanine, an oligothiophene, and/or a conjugated aromatic compound. The SAM layer may include a molecular structure having a first end group of a first monolayer, an intermediate group, a fifth end group of a second monolayer, and one or more of a first and second light-reflective moieties.

Abstract: An integrated circuit package comprising an integral structural member embedded within dielectric material and at least partially surrounding a keep-out zone of a co-planar package metallization layer. The integral structural member may increase stiffness of the package without increasing the package z-height. The structural member may comprise a plurality of intersecting elements. Individual structural elements may comprise conductive vias that are non-orthogonal to a plane of the package. An angle of intersection and thickness of the structural elements may be varied to impart more or less local or global rigidity to a package according to a particular package application. Intersecting openings may be patterned in a mask material by exposing a photosensitive material through a half-penta prism. Structural material may be plated or otherwise deposited into the intersecting openings.

Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.

Abstract: A conductive route for an integrated circuit assembly may be formed using a sequence of etching and passivation steps through layers of conductive material, wherein the resulting structure may include a first route portion having a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, an etch stop structure on the first route portion, a second route portion on the etch stop layer, wherein the second route portion has a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, and a passivating layer abutting the at least one side surface of the second route portion.

Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.

Abstract: Embodiments herein relate to systems, apparatuses, and/or processes directed to a package or a manufacturing process flow for creating a package that uses multiple seeding techniques to fill vias in the package. Embodiments include a first layer of copper seeding coupled with a portion of the boundary surface and a second layer of copper seeding coupled with the boundary surface or the first layer of copper seeding, where the first layer of copper seeding and the second layer of copper seeding have a combined thickness along the boundary surface that is greater than a threshold value.

Abstract: A device is disclosed. The device includes a first insulating film structure, a plurality of conductor layers above the first insulating film structure, a Ti structure and a nanocube structure between respective layers of the plurality of conductor layers, the nanocube structure above the Ti structure, and a second insulating film structure above a topmost conductor layer of the plurality of conductor layers.

Abstract: Embodiments include semiconductor packages and method of forming the semiconductor packages. A semiconductor package includes first waveguides over a package substrate. The first waveguides include first angled conductive layers, first transmission lines, and first cavities. The semiconductor package also includes a first dielectric over the first waveguides and package substrate, second waveguides over the first dielectric and first waveguides, and a second dielectric over the second waveguides and first dielectric. The second waveguides include second angled conductive layers, second transmission lines, and second cavities. The first angled conductive layers are positioned over the first transmission lines and package substrate having a first pattern of first triangular structures.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a first layer of a package substrate and a conductive trace over the first layer of the package substrate. In an embodiment, the conductive trace comprises a conductive body with a first surface over the first layer of the package substrate, a second surface opposite the first surface, and sidewall surfaces coupling the first surface to the second surface. In an embodiment, the second surface has a first roughness and the sidewall surfaces have a second roughness that is less than the first roughness.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a package substrate, a first die over the package substrate, the first die having a first bump pitch, a second die over the package substrate, the second die having a second bump pitch that is greater than the first bump pitch, and a plurality of conductive traces over the package substrate, the plurality of conductive traces electrically coupling the first die to the second die. In an embodiment, a first end region of the plurality of conductive traces proximate to the first die has a first line space (L/S) dimension, and a second end region of the plurality of conductive traces proximate to the second die has a second L/S dimension. In an embodiment, the second L/S dimension is greater than the first L/S dimension.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate having a first surface and a second surface opposite from the first surface, and a monolayer having a plurality of first molecules over the first surface of the package substrate. In an embodiment, the first molecules each comprise a first functional group attached to the first surface, and a first release moiety attached to the first functional group.

Abstract: An interconnection structure is disclosed. The interconnection structure includes a dielectric layer, an interfacial TiC layer on the dielectric layer, the interfacial TiC layer having a uniform thickness, and a Ti layer on the TiC layer.

Abstract: The present disclosure provides a substrate for an integrated circuit. The substrate includes a dielectric layer. The substrate further includes a plurality of conductive elements at least partially embedded within the dielectric layer and having a substantially smooth outer surface. The substrate further includes an interlayer disposed between the individual conductive elements and the dielectric layer. The interlayer has a first surface comprising a plurality of protrusions interlocked with the dielectric layer and a second surface adhered to the outer surface of the individual conductive elements.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a substrate and a conductive feature over the substrate. In an embodiment, a metallic mask is positioned over the conductive feature. In an embodiment, the metallic mask extends beyond a first edge of the conductive feature and a second edge of the conductive feature.