Abstract: A motion gesture sensing module includes a light source emitting light, and a light sensor unit including at least two optical detectors sensing light reflected from a subject, in which an optical block is disposed in a light receiving path of the light sensor unit and individually separates a detectable zone of each of the optical detectors, thereby determining a motion or gesture of the subject based on output of the light sensor unit. Further, a motion gesture sensing method is a contactless motion sensing method, in which a light source emits light, light reflected from a subject is received by at least two optical detectors, and output values of respective optical detectors are compared to determine a motion of a subject, thereby sensing motion gesture of the subject by individually separating a detectable zone of the optical detector and receiving the light reflected from the subject.

Abstract: A 3D semiconductor device and a method of manufacturing the same are provided. The 3D semiconductor device includes a semiconductor substrate, an insulating layer formed on the semiconductor substrate, an active line including a source region and a drain region formed on the insulating layer, a gate electrode located on a portion of the active line, corresponding to a region between the source region and the drain region, and extending to a direction substantially perpendicular to the active line, and a line-shaped common source node formed to be electrically coupled to the source region and extending substantially in parallel to the gate electrode in a space between gate electrodes.

Abstract: A 3D semiconductor device and a method of manufacturing the same are provided. The method includes forming a first semiconductor layer including a common source node on a semiconductor substrate, forming a transistor region on the first semiconductor layer, wherein the transistor region includes a horizontal channel region substantially parallel to a surface of the semiconductor substrate, and source and drain regions branched from the horizontal channel region to a direction substantially perpendicular to the surface of the semiconductor substrate, processing the first semiconductor layer to locate the common source node corresponding to the source region, forming a gate in a space between the source region and the drain region, forming heating electrodes on the source region and the drain region, and forming resistance variable material layers on the exposed heating electrodes.

Abstract: A semiconductor memory device includes a semiconductor substrate, an active region including a plurality of unit active regions and disposed over and spaced from the semiconductor substrate, a pair of word lines formed on a top surface and sides of the unit active region, a dummy word line disposed at a contact of the unit active regions and formed on top surfaces and sides of the unit active regions, a source region in the unit active region between the pair of word lines and electrically connected to the semiconductor substrate, drain regions formed in the unit active region between the pair of word lines and the dummy word line, and first storage layers formed on the drain regions and electrically connected to the drain regions.

Abstract: A semiconductor device forms a salicide layer to surround an upper surface and a circumference of a lateral surface of a pillar. A contact area between the pillar and a lower electrode may be increased to reduce a contact resistance.

Abstract: A 3D semiconductor device and a method of manufacturing the same are provided. The method includes forming a first semiconductor layer including a common source node on a semiconductor substrate, forming a transistor region on the first semiconductor layer, wherein the transistor region includes a horizontal channel region substantially parallel to a surface of the semiconductor substrate, and source and drain regions branched from the horizontal channel region to a direction substantially perpendicular to the surface of the semiconductor substrate, processing the first semiconductor layer to locate the common source node corresponding to the source region, forming a gate in a space between the source region and the drain region, forming heating electrodes on the source region and the drain region, and forming resistance variable material layers on the exposed heating electrodes.

Abstract: A semiconductor memory device includes a semiconductor substrate, an active region including a plurality of unit active regions and disposed over and spaced from the semiconductor substrate, a pair of word lines formed on a top surface and sides of the unit active region, a dummy word line disposed at a contact of the unit active regions and formed on top surfaces and sides of the unit active regions, a source region in the unit active region between the pair of word lines and electrically connected to the semiconductor substrate, drain regions formed in the unit active region between the pair of word lines and the dummy word line, and first storage layers formed on the drain regions and electrically connected to the drain regions.

Abstract: A semiconductor memory device includes a semiconductor substrate, an active region including a plurality of unit active regions and disposed over and spaced from the semiconductor substrate, a pair of word lines formed on a top surface and sides of the unit active region, a dummy word line disposed at a contact of the unit active regions and formed on top surfaces and sides of the unit active regions, a source region in the unit active region between the pair of word lines and electrically connected to the semiconductor substrate, drain regions formed in the unit active region between the pair of word lines and the dummy word line, and first storage layers formed on the drain regions and electrically connected to the drain regions.

Abstract: A semiconductor device is manufactured by, inter alia: forming second gate lines, arranged at wider intervals than each of first gate lines and first gate lines, over a semiconductor substrate; forming a multi-layered insulating layer over the entire surface of the semiconductor substrate including the first and the second gate lines; etching the multi-layered insulating layer so that a part of the multi-layered insulating layer remains between the first gate lines and the first and the second gate lines; forming mask patterns formed on the respective remaining multi-layered insulating layers and each formed to cover the multi-layered insulating layer between the second gate lines; and etching the multi-layered insulating layers remaining between the first gate lines and between the first and the second gate lines and not covered by the mask patterns so that the first and the second gate lines are exposed.

Abstract: A plasma display device and method of driving the device is disclosed. The device includes a driving circuit for driving reset, address, and sustain periods during a subfield of a frame. The driving circuit includes a single switch which is used to drive a display electrode both during the reset period and during the sustain period. The switch being used for both periods removes the need for a second switch, thereby reducing manufacturing and design costs.

Abstract: A semiconductor memory device includes a semiconductor substrate, an active region including a plurality of unit active regions and disposed over and spaced from the semiconductor substrate, a pair of word lines formed on a top surface and sides of the unit active region, a dummy word line disposed at a contact of the unit active regions and formed on top surfaces and sides of the unit active regions, a source region in the unit active region between the pair of word lines and electrically connected to the semiconductor substrate, drain regions formed in the unit active region between the pair of word lines and the dummy word line, and first storage layers formed on the drain regions and electrically connected to the drain regions.

Abstract: A semiconductor device is manufactured by, inter alia: forming second gate lines, arranged at wider intervals than each of first gate lines and first gate lines, over a semiconductor substrate; forming a multi-layered insulating layer over the entire surface of the semiconductor substrate including the first and the second gate lines; etching the multi-layered insulating layer so that a part of the multi-layered insulating layer remains between the first gate lines and the first and the second gate lines; forming mask patterns formed on the respective remaining multi-layered insulating layers and each formed to cover the multi-layered insulating layer between the second gate lines; and etching the multi-layered insulating layers remaining between the first gate lines and between the first and the second gate lines and not covered by the mask patterns so that the first and the second gate lines are exposed.

Abstract: In a plasma display device, a secondary coil of a transformer is connected across a panel capacitor formed by a scan electrode and a sustain electrode performing a sustain discharge. The plasma display device uses resonance between a secondary coil of a transformer and a panel capacitor to apply a sustain discharge pulse to a scan electrode and a sustain electrode in a sustain period.

Abstract: An interface system capable of reducing or minimizing an electromagnetic interference. The interface system includes a serializing unit for receiving first data having a plurality of bits and second data having a plurality of bits, and for serially outputting the plurality of bits of the received first data and second data as 2 bits; a transmission circuit for generating 4 voltage levels in accordance with the 2 bits supplied from the serializing unit; a receiving circuit for recovering the 2 bits using the voltage levels supplied from the transmission circuit; and a deserializing unit for recovering the first data and the second data while sequentially storing the 2 bits supplied from the receiving circuit.

Abstract: Provided are a protecting layer for a plasma display panel (PDP), a method of forming the same, and a PDP including the protecting layer. The protecting layer includes a magnesium oxide-containing layer having a surface to which magnesium oxide-containing particles having a magnesium vacancy-impurity center (VIC) are attached. The protecting layer is resistant to plasma ions and has excellent electron emission effects, and thus, a PDP including the protecting layer can be operated at low voltage with high discharge efficiency.

Abstract: A method of driving a plasma display device having a first electrode and a second electrode adjacent to one another in a discharge cell, including applying a first waveform at least once to the first electrode, the first waveform including a gradual increase from a first voltage to a second voltage followed by a gradual decrease from a third voltage to a fourth voltage, and applying a second waveform at least once to the first electrode after the first waveform is applied to the first electrode, the second waveform including a gradual increase from a fifth voltage to a sixth voltage followed by a gradual decrease from a seventh voltage to an eighth voltage. The first and second waveforms may be applied to the first electrode after turning on the plasma display device and before a display operation is performed.

Abstract: In a plasma display device, a secondary coil of a transformer is connected across a panel capacitor formed by a scan electrode and a sustain electrode performing a sustain discharge. The plasma display device uses resonance between a secondary coil of a transformer and a panel capacitor to apply a sustain discharge pulse to a scan electrode and a sustain electrode in a sustain period.

Abstract: A plasma display is disclosed. In the plasma display, a first transistor for applying a low level voltage of a sustain pulse is connected to a high voltage terminal of a scanning circuit and a second transistor for applying a high level voltage of the sustain pulse is connected to a low voltage terminal of the scanning circuit. The first and the second transistors are alternatively turned on during sustain period, and the sustain pulse is applied to the scan electrode.

Abstract: A plasma display device including a plasma display panel (PDP), a temperature detector for detecting temperature of the PDP, a driver for applying a driving voltage to a scan electrode, and a controller for generating a control signal to control the driver according to the temperature. The driver includes a transistor and first and second resistors. The transistor is coupled between a first power source and the scan electrode. The first power source supplies a scan voltage to the scan electrode. At least one of the first resistor and the second resistor is a variable resistor having a resistance that varies according to the control signal of the controller. A low discharge due to high temperature can be reduced or prevented, and the number of power sources of the plasma display device can be reduced.

Abstract: A plasma display apparatus includes: an electrode of a discharge cell; a first transistor having a first terminal and a second terminal, the second terminal being connected to the electrode; a first capacitor having a first terminal to receive a control signal having either a low level voltage or a high level voltage; a push-pull circuit including a first power terminal, a second power terminal connected to the first terminal of the first transistor, an input terminal connected to a second terminal of the first capacitor, and an output terminal connected to a gate of the first transistor, the push-pull circuit outputting either a voltage of the first power terminal or a voltage of the second power terminal to the output terminal; a floating power source having a positive terminal connected to the first power terminal and a negative terminal connected to the second power terminal; and a first diode connected between the first terminal of the first transistor and the second terminal of the first capacitor.