Abstract: A protecting layer of a Plasma Display Panel (PDP) is composed of metal and metal oxide. The metal is disposed away from the surface of the protecting layer by 10% or less than the thickness of the protecting layer. Furthermore, in a method of forming the protecting layer for a PDP and in a PDP employing the protecting layer, the metal is disposed away from the surface of the protecting layer by 10% or less than the thickness of the protecting layer.

Abstract: Provided are a protective layer made of magnesium oxide containing at least one rare earth element selected from the group consisting of the rare earth elements, in which the content of the at least one rare earth element is from about 5.0×10?5 to about 6.0×10?4 per 1 part by weight of the magnesium oxide, a composite for forming the protective layer, a method of forming the protective layer, and a plasma display panel including the protective layer. The protective layer can reduce a discharge delay time and the temperature dependency of the discharge delay time, and thus, is suitable for single scan and an increase in Xe content.

Abstract: Herein is provided a protective layer for a plasma display panel and a method of forming the protective layer. The protective layer is formed on a substrate of the plasma display panel which includes sustain electrodes. Grain columns having directionality are formed in the texture of the protective layer. Because the direction of the grain columns can be controlled, the general orientation of the voids is known, and an electric field can be applied for discharge in a direction where the number of voids is smallest. As a result, the etching rate of the protective layer can be reduced, thereby increasing the lifetime of the protective layer. In addition, since discharge ions are less likely to impact the protective layer rapid emission of secondary electrons and reduced discharge delay time is realized. It is therefore possible to shorten the discharge delay time and to improve the breakdown voltage of discharge.

Abstract: A data recovery circuit and a method thereof, which are capable of reducing locking time and jitter, are provided. The data recovery circuit includes a frequency-locked loop, a locking detector, a delay-locked loop, and a data determination circuit. The frequency-locked loop locks the frequency of an internal clock signal fed back thereto in response to an input signal with the frequency of the input signal and generates a frequency locking signal representing that the input signal is frequency-locked with the internal clock signal. The locking detector determines whether the frequency of the internal clock signal is in a predetermined frequency range of the input signal in response to the frequency locking signal and generates a phase control signal. The delay-locked loop is controlled by the phase control signal, locks the phase of the internal clock signal with the phase of the input signal, and generates a recovery locking signal.

Abstract: Disclosed is an infrared remote control receiver comprising a photo diode for converting an optical signal to an electrical signal, a semiconductor signal processing device for receiving the electrical from the photo diode, eliminating noise components from the electrical signal output from the photo diode and generating a pulse signal corresponding to a remote control signal transmitted from a remote control transmission device, and a micro computer for receiving the pulse signal from the semiconductor signal processing device and performing a remote control operation instructed by a user of the remote control transmission device by decoding the received pulse signal, wherein the semiconductor signal processing device is fabricated using CMOS devices fabrication processes.

Abstract: A data recovery circuit and a method thereof, which are capable of reducing locking time and jitter, are provided. The data recovery circuit includes a frequency-locked loop, a locking detector, a delay-locked loop, and a data determination circuit. The frequency-locked loop locks the frequency of an internal clock signal fed back thereto in response to an input signal with the frequency of the input signal and generates a frequency locking signal representing that the input signal is frequency-locked with the internal clock signal. The locking detector determines whether the frequency of the internal clock signal is in a predetermined frequency range of the input signal in response to the frequency locking signal and generates a phase control signal. The delay-locked loop is controlled by the phase control signal, locks the phase of the internal clock signal with the phase of the input signal, and generates a recovery locking signal.

Abstract: A cathode for a cathode ray tube includes a base having a closed top portion and containing nickel as its main component, an electron-emitting material layer coated on the top portion of the base and containing alkali-earth metal oxides as its main component, rare-earth metals or rare-earth metal compounds attached on a surface of the electron-emitting material layer, and a heater placed under the top portion of the base to heat it.

Abstract: A digital data storage system which does not require the use of moving, mechanical components, and which utilizes semiconductor memory elements, thereby improving the reliability and extending the useful life thereof, and also minimizing the cost, complexity, and size thereof relative to conventional digital data storage systems, such as CD players and DAT devices. In a playback only embodiment, the digital data storage system includes a ROM, a system control microcomputer, a digital signal processor (DSP), and a D/A converter. In operation, the DSP is responsive to control signals generated by the system control microcomputer for reading out digital data, e.g., digital audio data, stored in the ROM, and decoding the read-out digital data. The D/A converter functions to convert the decoded read-out digital data into an analog output signal, e.g., an analog audio signal, and to supply the analog output signal to an output terminal.

Abstract: In a noise canceler, a pilot-canceling signal without noise is applied to the inverting input of a subtracter via a first MOS transistor. When a noise signal is present, a pilot signal and noise signal passing through a capacitor are applied to the inverting input port of the subtracter via a second MOS transistor to cancel the noise signal contained in the composite input signal. In the canceler, external noise may be digitally converted and the inverted noise thereof stored in a memory. When a noise signal detector detects the external noise, inverted data corresponding to the external noise is output from the memory. The detector enables an address generator to continuously generate addresses. The memory reads out inverted noise patterns which are converted into analog form and transmitted via a speaker, thereby canceling noises produced by various electrical and electronic appliances as well as nearby automobiles and aircraft.

Abstract: A digital data storage system which does not require the use of moving, mechanical components, and which utilizes semiconductor memory elements. In one embodiment, the digital data storage system includes a ROM, a system control microcomputer, a digital signal processor (DSP), and a D/A converter. In operation, the DSP is responsive to control signals generated by the system control microcomputer for reading out digital data, e.g., digital audio data, stored in the ROM, and decoding the read-out digital data. The D/A converter functions to convert the decoded read-out digital data into an analog output signal, e.g., an analog audio signal, and to supply the analog output signal to an output terminal. The digital data storage system of this embodiment is a playback-only system. In another embodiment, the digital data storage system includes all of the elements of the above-described embodiment, and further includes an A/D converter and an EEPROM, to facilitate the recording of digital data.

Abstract: A floating detection circuit detects the floating state of an input node which can receive an externally applied DC input signal, and includes a pulse generator, a counter and a floating state discriminator. The pulse generator is coupled to the input node and supplies a pulse signal to the input node when the input node is in a floating state. The counter receives the pulse signal and counts the number of pulses included in the pulse signal during predetermined intervals. The floating state discriminator compares the number of pulses with a predetermined reference number, so as to produce a floating detection signal, wherein the floating detection signal indicates whether or not the input node is in a floating state. A semiconductor circuit includes this floating detection circuit and a DC level detector. The floating detection circuit included in the semiconductor circuit detects the input node state during a first period and produces the floating detection signal during a second period.

Abstract: In a noise canceler, a pilot-canceling signal without noise is applied to the inverting input of a subtracter via a first MOS transistor. When a noise signal is present, a pilot signal and noise signal passing through a capacitor are applied to the inverting input port of the subtracter via a second MOS transistor to cancel the noise signal contained in the composite input signal. In the canceler, external noise may be digitally converted and the inverted noise thereof stored in a memory. When a noise signal detector detects the external noise, inverted data corresponding to the external noise is output from the memory. The detector enables an address generator to continuously generate addresses. The memory reads out inverted noise patterns which are converted into analog form and transmitted via a speaker, thereby canceling noises produced by various electrical and electronic appliances as well as nearby automobiles and aircraft.

Abstract: An improved dual slope integrating analog-to-digital converter for use in a Digital Multi-Meter includes an input portion, an A/D core portion, and a digital portion. The A/D core portion includes an auto zero function capability for automatically compensating for any existing offset voltages in various measurement modes such as voltage, resistance, or current measurement modes. The improved A/D converter of the present invention operates at high speed and with high resolution.