Abstract: A plasma display device including a plasma display panel (PDP), a temperature detector for detecting temperature of the PDP, a driver for applying a driving voltage to a scan electrode, and a controller for generating a control signal to control the driver according to the temperature. The driver includes a transistor and first and second resistors. The transistor is coupled between a first power source and the scan electrode. The first power source supplies a scan voltage to the scan electrode. At least one of the first resistor and the second resistor is a variable resistor having a resistance that varies according to the control signal of the controller. A low discharge due to high temperature can be reduced or prevented, and the number of power sources of the plasma display device can be reduced.

Abstract: A protecting layer is formed of a magnesium oxide and at least one additional component selected from the group consisting of a copper component selected from copper and a copper oxide, a nickel component selected from nickel and a nickel oxide, a cobalt component selected from cobalt and a cobalt oxide, and an iron component selected from iron and an iron oxide; a composite for forming the protecting layer; a method of forming the protecting layer; and a plasma display panel including the protecting layer. The protecting layer, which is used in a PDP, protects an electrode and a dielectric layer from a plasma ion generated by a gaseous mixture of Ne and Xe, or He, Ne, and Xe, and discharge delay time and dependency of the discharge delay time on temperature can be decreased and sputtering resistance can be increased.

Abstract: An interface system capable of minimizing an electro magnetic interference.

Abstract: An interface system capable of reducing or minimizing an electromagnetic interference. The interface system includes a serializing unit for receiving first data having a plurality of bits and second data having a plurality of bits, and for serially outputting the plurality of bits of the received first data and second data as 2 bits; a transmission circuit for generating 4 voltage levels in accordance with the 2 bits supplied from the serializing unit; a receiving circuit for recovering the 2 bits using the voltage levels supplied from the transmission circuit; and a deserializing unit for recovering the first data and the second data while sequentially storing the 2 bits supplied from the receiving circuit.

Abstract: The sintered magnesium oxide according to one embodiment has a density of less than 3.5 g/cm3 and an average grain size of about 3 to about 10 ?m. A MgO protective layer made from the sintered magnesium oxide reduces a discharge voltage of a plasma display panel, improves its response speed, and provides it with high-purity film quality.

Abstract: A material for preparing a protective layer for a PDP, which reduces discharge delay time, improves temperature dependency, and has enhanced ion strength; a method of preparing the same; a protective layer formed of the material; and a PDP including the protective layer. More particularly, a material for a protective layer that includes monocrystalline magnesium oxide doped with a rare earth element at an amount of 2.0×10?5?1.0×10?2 parts by weight per 1 part by weight of magnesium oxide (MgO), a method of preparing the monocrystalline magnesium oxide by crystallizing it at about 2,800° C., a protective layer formed of the same, and PDP including the protective layer.

Abstract: A sintered magnesium oxide has a density of 3.5 g/cm3 or more, and has a grain size that is more than or equal to thirty times the average particle diameter of magnesium oxide particles. An MgO protective layer made from the sintered magnesium oxide reduces a discharge voltage of a plasma display panel, improves response speed, and provides a high-purity film quality.

Abstract: A plasma display device and a driving method thereof. The plasma display device includes drivers for scan, sustain and address electrodes and a controller for controlling the drivers. The scan electrode driver includes a capacitor whose charge is proportional to an on period of a switch included in the driver circuit or may be otherwise controlled. By controlling the charge of the capacitor, a voltage difference between the reset falling voltage and the select voltage that are applied to the scan electrodes during the reset and subsequent address periods can be controlled to control the discharge margin and to correspond to the design of the plasma display device. The need for a Zener diode with a high withstand voltage is alleviated.

Abstract: A driving device for a plasma display panel including a plurality of address electrodes extending along a column direction and scan electrodes and sustain electrodes sequentially arranged in and extending along a row direction, the driving device being for applying a driving voltage to the scan electrodes and including: a falling reset unit for applying a gradually falling voltage from Vs voltage to the lowest voltage Vnf to the scan electrodes, during the falling ramp period; and a scan driver being for sequentially applying scan voltage VscL lower than the Vnf voltage by ?V to the scan electrodes in the address period, wherein the falling reset unit includes a falling ramp switch, a diode, and a Zener diode, which are connected in series.

Abstract: An apparatus for driving a plasma display panel comprises: a plasma display panel including a plurality of scan electrodes, a plurality of sustain electrodes, and a plurality of address electrodes formed in a direction so as to cross the scan electrodes and the sustain electrodes; a plurality of scan ICs connected to each of a plurality of scan electrode groups into which the scan electrodes are classified according to specific references for controlling whether or not a driving signal is applied by means of first and second output control terminals; a plurality of first output control terminal groups for connecting a first output control terminal which is classified according to the first reference out of the specific references; a plurality of second output control terminal groups for connecting a second output control terminal which is classified according to the second reference out of the specific references; and a controller for applying a high level signal or a low level signal to a plurality of the fi

Abstract: A plasma display apparatus includes: an electrode of a discharge cell; a first transistor having a first terminal and a second terminal, the second terminal being connected to the electrode; a first capacitor having a first terminal to receive a control signal having either a low level voltage or a high level voltage; a push-pull circuit including a first power terminal, a second power terminal connected to the first terminal of the first transistor, an input terminal connected to a second terminal of the first capacitor, and an output terminal connected to a gate of the first transistor, the push-pull circuit outputting either a voltage of the first power terminal or a voltage of the second power terminal to the output terminal; a floating power source having a positive terminal connected to the first power terminal and a negative terminal connected to the second power terminal; and a first diode connected between the first terminal of the first transistor and the second terminal of the first capacitor.

Abstract: A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate having a field oxide layer, etching the substrate to form a recess by using the hard mask pattern, forming a first conductive layer over the recess and the hard mask pattern, planarizing the first conductive layer, and forming a second conductive layer over the planarized first conductive layer.

Abstract: A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate, forming a first recess in the substrate and a passivation layer on sidewalls of the first recess using the hard mask pattern as an etch barrier, and forming a second recess by etching a bottom portion of the first recess using the passivation layer as an etch barrier, wherein a width of the second recess is greater than that of the first recess.

Abstract: A method of fabricating a semiconductor device includes forming a hard mask pattern over a substrate, wherein the hard mask pattern exposes a recess region, performing a first etching process on the exposed recess region to form a first recess having sidewalls and to form passivation layers on the sidewalls of the first recess wherein the passivation layers are comprised of an etch reactant of the first etching process, and performing a second etching process on the substrate below the first recess to form a second recess.

Abstract: In a plasma display, a first electrode and a second electrode of a transistor may be respectively coupled to a scan electrode and a power source for supplying a scan voltage. The plasma display may include a scan electrode, a first transistor, a first resistor, and a second resistor. The first transistor may include a first electrode electrically coupled to the scan electrode, a second electrode electrically coupled to the power source and a control electrode. The first resistor may be electrically coupled between the scan electrode and the control electrode of the first transistor. The second resistor may be electrically coupled between the control electrode of the transistor and the power source.

Abstract: In a plasma display and a voltage generator thereof, a first electrode of a transistor is coupled to a scan electrode. In addition, a cathode of a Zener diode is coupled to a second electrode of the transistor, and an anode of the Zener diode is coupled to a power source generating a scan voltage. A first resistor is coupled between the first electrode of the transistor and a control electrode of the transistor, and a second resistor is coupled between the control electrode of the transistor and the anode of the Zener diode. A final voltage during a reset period is generated by the power source generating the scan voltage.

Abstract: A method for fabricating a semiconductor device with a bulb shaped recess gate pattern includes selectively etching a first portion of a substrate to form a first recess; forming a spacer on sidewalls of the first recess; performing an isotropic etching process on a second portion of the substrate beneath the first recess to form a second recess, the second recess being wider and more rounded than the first recess; removing the spacer; and forming a gate pattern having a first portion buried into the first and second recesses and a second portion projecting over the substrate.

Abstract: Disclosed is an infrared remote control receiver comprising a photo diode for converting an optical signal to an electrical signal, a semiconductor signal processing device for receiving the electrical from the photo diode, eliminating noise components from the electrical signal output from the photo diode and generating a pulse signal corresponding to a remote control signal transmitted from a remote control transmission device, and a micro computer for receiving the pulse signal from the semiconductor signal processing device and performing a remote control operation instructed by a user of the remote control transmission device by decoding the received pulse signal, wherein the semiconductor signal processing device is fabricated using CMOS devices fabrication processes.

Abstract: A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and filled in the openings; etching the first conductive layer to form interconnection layers in the openings and to expose portions of the metal barrier layer, the interconnection layers being inside the openings and at a depth from a top of the openings; etching the exposed portions of the metal barrier layer to obtain a sloped profile of the metal barrier layer at top lateral portions of the openings; forming a second conductive layer over the inter-layer insulation layer, the interconnection layers and the metal barrier layer with the sloped profile; and patterning the second conductive layer to form metal lines.

Abstract: A protecting layer is formed of a magnesium oxide and at least one additional component selected from the group consisting of a copper component selected from copper and a copper oxide, a nickel component selected from nickel and a nickel oxide, a cobalt component selected from cobalt and a cobalt oxide, and an iron component selected from iron and an iron oxide; a composite for forming the protecting layer; a method of forming the protecting layer; and a plasma display panel including the protecting layer. The protecting layer, which is used in a PDP, protects an electrode and a dielectric layer from a plasma ion generated by a gaseous mixture of Ne and Xe, or He, Ne, and Xe, and discharge delay time and dependency of the discharge delay time on temperature can be decreased and sputtering resistance can be increased.