Abstract: The invention includes methods of forming field effect transistors. In one implementation, a method of forming a field effect transistor having a gate comprising a conductive metal or metal compound received over conductively doped semiconductive material includes forming transistor gate semiconductive material into a gate line over a semiconductive material channel region. The gate line includes semiconductive material sidewalls. The semiconductive material sidewalls of the gate line are oxidized. After the oxidizing, at least one of a conductive metal or metal compound is formed in electrical connection with the transistor gate semiconductive material to comprise a substantially coextensive elongated portion of a final construction of the gate line of the field effect transistor being formed.

Abstract: A first dielectric layer is formed over a substrate. A single layer first conductive layer that acts as a floating gate is formed over the first dielectric layer. A trough is formed in the first conductive layer to increase the capacitive coupling of the floating gate with a control gate. An intergate dielectric layer is formed over the floating gate layer. A second conductive layer is formed over the second dielectric layer to act as a control gate.

Abstract: A method for forming a semiconductor device comprises forming a layer to be etched, then forming a hard mask layer over the layer to be etched. The hard mask is etched to form an opening defined by first and second cross-sectional sidewalls in the hard mask layer. In one embodiment, the opening in the hard mask layer is formed at the minimum limits allowable by optical lithography. A conformal spacer layer is formed over the hard mask layer and on the sidewalls of the hard mask, then spacer etched to form first and second cross-sectional spacers along the first and second sidewalls in the patterned hard mask layer. The hard mask and spacers are preferably formed from amorphous carbon. The layer to be etched is etched using the hard mask layer and the spacers as a pattern, then the hard mask layer and spacers are removed.

Abstract: A method for forming a semiconductor device comprises forming a layer to be etched, then forming a hard mask layer over the layer to be etched. The hard mask is etched to form an opening defined by first and second cross-sectional sidewalls in the hard mask layer. In one embodiment, the opening in the hard mask layer is formed at the minimum limits allowable by optical lithography. A conformal spacer layer is formed over the hard mask layer and on the sidewalls of the hard mask, then spacer etched to form first and second cross-sectional spacers along the first and second sidewalls in the patterned hard mask layer. The hard mask and spacers are preferably formed from amorphous carbon. The layer to be etched is etched using the hard mask layer and the spacers as a pattern, then the hard mask layer and spacers are removed.

Abstract: Methods of fabrication and flash memory structures eliminate process steps while increasing capacitive coupling between floating gates and control gates of the memory cells. A thick floating gate is deposited early in the process, and a height and width of the floating gate is controlled with deposition and etching or the use of spacers.

Abstract: Methods of fabrication and flash memory structures eliminate process steps while increasing capacitive coupling between floating gates and control gates of the memory cells. A thick floating gate is deposited early in the process, and a height and width of the floating gate is controlled with deposition and etching or the use of spacers.

Abstract: A first dielectric layer is formed over a substrate. A single layer first conductive layer that acts as a floating gate is formed over the first dielectric layer. A trough is formed in the first conductive layer to increase the capacitive coupling of the floating gate with a control gate. An intergate dielectric layer is formed over the floating gate layer. A second conductive layer is formed over the second dielectric layer to act as a control gate.

Abstract: The invention includes methods of forming field effect transistors. In one implementation, a method of forming a field effect transistor having a gate comprising a conductive metal or metal compound received over conductively doped semiconductive material includes forming transistor gate semiconductive material into a gate line over a semiconductive material channel region. The gate line includes semiconductive material sidewalls. The semiconductive material sidewalls of the gate line are oxidized. After the oxidizing, at least one of a conductive metal or metal compound is formed in electrical connection with the transistor gate semiconductive material to comprise a substantially coextensive elongated portion of a final construction of the gate line of the field effect transistor being formed.

Abstract: A novel technique to quench electrical defects in CVD Al2O3 layers is disclosed. A small amount of silicon dopant to the aluminum oxide film reduces the leakage current as well as the gap interface trap density at the dielectric/silicon interface. The implanted silicon gives a better interface and improves the leakage characteristics of the dielectric.

Abstract: A method for forming a semiconductor device comprises forming a layer to be etched, then forming a hard mask layer over the layer to be etched. The hard mask is etched to form an opening defined by first and second cross-sectional sidewalls in the hard mask layer. In one embodiment, the opening in the hard mask layer is formed at the minimum limits allowable by optical lithography. A conformal spacer layer is formed over the hard mask layer and on the sidewalls of the hard mask, then spacer etched to form first and second cross-sectional spacers along the first and second sidewalls in the patterned hard mask layer. The hard mask and spacers are preferably formed from amorphous carbon. The layer to be etched is etched using the hard mask layer and the spacers as a pattern, then the hard mask layer and spacers are removed.

Abstract: The invention includes methods of forming field effect transistors. In one implementation, a method of forming a field effect transistor having a gate comprising a conductive metal or metal compound received over conductively doped semiconductive material includes forming transistor gate semiconductive material into a gate line over a semiconductive material channel region. The gate line includes semiconductive material sidewalls. The semiconductive material sidewalls of the gate line are oxidized. After the oxidizing, at least one of a conductive metal or metal compound is formed in electrical connection with the transistor gate semiconductive material to comprise a substantially coextensive elongated portion of a final construction of the gate line of the field effect transistor being formed.

Abstract: The invention includes methods of forming field effect transistors. In one implementation, a method of forming a field effect transistor having a gate comprising a conductive metal or metal compound received over conductively doped semiconductive material includes forming transistor gate semiconductive material into a gate line over a semiconductive material channel region. The gate line includes semiconductive material sidewalls. The semiconductive material sidewalls of the gate line are oxidized. After the oxidizing, at least one of a conductive metal or metal compound is formed in electrical connection with the transistor gate semiconductive material to comprise a substantially coextensive elongated portion of a final construction of the gate line of the field effect transistor being formed.

Abstract: A novel technique to quench electrical defects in CVD Al2O3 layers is disclosed. A small amount of silicon dopant to the aluminum oxide film reduces the leakage current as well as the gap interface trap density at the dielectric/silicon interface. The implanted silicon gives a better interface and improves the leakage characteristics of the dielectric.

Abstract: A novel technique to quench electrical defects in CVD Al2O3 layers is disclosed. A small amount of silicon dopant to the aluminum oxide film reduces the leakage current as well as the gap interface trap density at the dielectric/silicon interface. The implanted silicon gives a better interface and improves the leakage characteristics of the dielectric.

Abstract: A split-gate transistor having high coupling for use in flash memory, EPROMs, and EEPROMs. The transistor has a U-shaped floating gate and a U-shaped control gate, thereby significantly increasing the surface area of the gates and increasing the voltage coupling ratio. The high coupling permits the operation voltage to be reduced while increasing operation speed, and the configuration of the transistor gates allows their use in high density arrays without sacrificing speed or degrading operations. A process for forming such transistors is also disclosed, wherein a polysilicon layer is deposited and then etched so that nitride and polysilicon spacers may be formed in between portions of polysilicon which are then etched to form floating gates. The nitride portion of the spacers is removed, and then the dielectric and control gate layers are formed on the floating gates to yield an array of split-gate transistors.

Abstract: A method of forming a coupling dielectric in a memory cell includes forming an oxide on a substrate, forming Ta2O5 on the oxide, oxidizing the Ta2O5 with rapid thermal process (RTP) at a temperature above the crystallization temperature for Ta2O5, forming a cell nitride on the oxidized Ta2O5, and forming a wetgate oxide on the cell nitride.

Abstract: A dielectric sandwich for use in a memory device is disclosed. The dielectric sandwich is thin and has at least one high permittivity layer having a thickness of between 140 and 240 angstroms. The dielectric sandwich also has at least one oxide layer formed at a temperature above the crystallization temperature of the high permittivity layer. In a flash memory cell the dielectric sandwich is located between the control gate and the floating gate and provides tight coupling between the control gate and the floating gate.

Abstract: A split-gate transistor having high coupling for use in flash memory, EPROMs, and EEPROMs. The transistor has a U-shaped floating gate and a U-shaped control gate, thereby significantly increasing the surface area of the gates and increasing the voltage coupling ratio. The high coupling permits the operation voltage to be reduced while increasing operation speed, and the configuration of the transistor gates allows their use in high density arrays without sacrificing speed or degrading operations. A process for forming such transistors is also disclosed, wherein a polysilicon layer is deposited and then etched so that nitride and polysilicon spacers may be formed in between portions of polysilicon which are then etched to form floating gates. The nitride portion of the spacers is removed, and then the dielectric and control gate layers are formed on the floating gates to yield an array of split-gate transistors.

Abstract: The invention includes methods of forming field effect transistors. In one implementation, a method of forming a field effect transistor having a gate comprising a conductive metal or metal compound received over conductively doped semiconductive material includes forming transistor gate semiconductive material into a gate line over a semiconductive material channel region. The gate line includes semiconductive material sidewalls. The semiconductive material sidewalls of the gate line are oxidized. After the oxidizing, at least one of a conductive metal or metal compound is formed in electrical connection with the transistor gate semiconductive material to comprise a substantially coextensive elongated portion of a final construction of the gate line of the field effect transistor being formed.

Abstract: A split-gate transistor having high coupling for use in flash memory, EPROMs, and EEPROMs. The transistor has a U-shaped floating gate and a U-shaped control gate, thereby significantly increasing the surface area of the gates and increasing the voltage coupling ratio. The high coupling permits the operation voltage to be reduced while increasing operation speed, and the configuration of the transistor gates allows their use in high density arrays without sacrificing speed or degrading operations. A process for forming such transistors is also disclosed, wherein a polysilicon layer is deposited and then etched so that nitride and polysilicon spacers may be formed in between portions of polysilicon which are then etched to form floating gates. The nitride portion of the spacers is removed, and then the dielectric and control gate layers are formed on the floating gates to yield an array of split-gate transistors.