Abstract: A formed body of Cu—Al—Mn-based shape-memory alloy may include a screw portion, wherein the screw portion is a form-rolled portion. A method for producing a formed body of Cu—Al—Mn-based shape-memory alloy may involve forming a screw portion having superelasticity by plastically working at least a portion of a material for the formed body with form-rolling in a state that a crystal structure is an A2-type structure and then, subjecting heat-treatment so as to convert the A2-type crystal structure into an L21-type crystal structure. The screw portion can be formed with good working property, and has excellent fatigue resistance and breaking resistance.

Abstract: A vehicle control apparatus includes a detection section, a control section. The detection section is configured to detect vehicle information including a vehicle speed of a vehicle driven by an electric motor and drive torque of the electric motor. The control section is configured to moderate a rate of increase in the drive torque at the time of acceleration with respect to a rate of increase set in advance on the basis of a detection result of the detection section on condition that the vehicle speed of the vehicle is less than or equal to a predetermined speed and the drive torque is greater than or equal to a predetermined threshold.

Abstract: A vehicle control apparatus includes a detection section, a control section. The detection section is configured to detect vehicle information including a vehicle speed of a vehicle driven by an electric motor and drive torque of the electric motor. The control section is configured to moderate a rate of increase in the drive torque at the time of acceleration with respect to a rate of increase set in advance on the basis of a detection result of the detection section on condition that the vehicle speed of the vehicle is less than or equal to a predetermined speed and the drive torque is greater than or equal to a predetermined threshold.

Abstract: An apparatus for estimating temperatures of a vehicle includes an acquirer to acquire an engine correlated temperature correlated with the temperature of an engine when the engine is stopping. The apparatus further includes an estimator to estimate a catalyst temperature of a catalyst disposed in an exhaust system of the engine, based on an inlet gas temperature estimated through a first-order lag operation with an exhaust-manifold temperature at a stop of the engine as an initial temperature and the engine correlated temperature as a target temperature.

Abstract: An engine operation control device for a hybrid vehicle, including: an engine provided in a vehicle; a power generator that is driven by the engine to generate electric power; a driving battery that is chargeable with electric power supplied from the power generator; and a front motor and a rear motor that drive wheels with electric power supplied from the driving battery or the power generator, and allowing a series mode in which the front motor drives front wheels and the rear motor drives rear wheels while the engine is operated at a predetermined set rotational speed to drive the power generator to generate electric power, wherein the set rotational speed is set to increase with decreasing of the atmospheric pressure in a present position of the vehicle in the series mode.

Abstract: An apparatus for estimating temperatures of a vehicle includes an acquirer to acquire an engine correlated temperature correlated with the temperature of an engine when the engine is stopping. The apparatus further includes an estimator to estimate a catalyst temperature of a catalyst disposed in an exhaust system of the engine, based on an inlet gas temperature estimated through a first-order lag operation with an exhaust-manifold temperature at a stop of the engine as an initial temperature and the engine correlated temperature as a target temperature.

Abstract: A traveling mode switching controller of a hybrid electric vehicle has a state-of-charge detection unit; a driver request output detection unit; a correction unit; and a switching control unit for controlling a switch from a first traveling mode to a second traveling mode when a vehicle request output exceeds an output threshold value. In the first traveling mode, an engine is deactivated and the drive motor is activated. In the second traveling mode, drive wheels are actuated by means of driving power of the engine, or a generator connected to the engine is activated to generate electric power to activate the drive motor to actuate the drive wheels. The switching control unit sets the output threshold value low as the state of charge decreases, thereby changing conditions for switching the first traveling mode to the second traveling mode.

Abstract: An engine operation control device for a hybrid vehicle, including: an engine provided in a vehicle; a power generator that is driven by the engine to generate electric power; a driving battery that is chargeable with electric power supplied from the power generator; and a front motor and a rear motor that drive drive wheels with electric power supplied from the driving battery or the power generator, and allowing a series mode in which the front motor drives front wheels and the rear motor drives rear wheels while the engine is operated at a predetermined set rotational speed to drive the power generator to generate electric power, wherein the set rotational speed is set to increase with decreasing of the atmospheric pressure in a present position of the vehicle in the series mode.

Abstract: A traveling mode switching controller of a hybrid electric vehicle has a state-of-charge detection unit; a driver request output detection unit; a correction unit; and a switching control unit for controlling a switch from a first traveling mode to a second traveling mode when a vehicle request output exceeds an output threshold value. In the first traveling mode, an engine is deactivated and the drive motor is activated. In the second traveling mode, drive wheels are actuated by means of driving power of the engine, or a generator connected to the engine is activated to generate electric power to activate the drive motor to actuate the drive wheels. The switching control unit sets the output threshold value low as the state of charge decreases, thereby changing conditions for switching the first traveling mode to the second traveling mode.

Abstract: A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

Abstract: A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

Abstract: A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

Abstract: A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

Abstract: A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

Abstract: A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

Abstract: A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

Abstract: A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

Abstract: In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval. With such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.

Abstract: A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

Abstract: A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.