Patents by Inventor Sumio Tanaka

Sumio Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10351939
    Abstract: A Cu—Al—Mn-based alloy having superelastic characteristics and having a recrystallized texture substantially formed of a ? single phase, in which 70% or more of crystal grains is within a range of 0° to 50° in a deviation angle from <001> orientation of a crystalline orientation measured in a working direction by electron back-scatter diffraction patterning.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: July 16, 2019
    Assignees: TOHOKU UNIVERSITY, FURUKAWA TECHNO MATERIAL CO., LTD., FURUKAWA ELECTRIC CO., LTD.
    Inventors: Toshihiro Omori, Shingo Kawata, Ryosuke Kainuma, Kiyohito Ishida, Toyonobu Tanaka, Kenji Nakamizo, Sumio Kise, Koji Ishikawa, Misato Nakano, Satoshi Teshigawara
  • Publication number: 20190153571
    Abstract: A Fe-based shape memory alloy material, containing 25 atom % to 42 atom % of Mn, 9 atom % to 13 atom % of Al, 5 atom % to 12 atom % of Ni, and 5.1 atom % to 15 atom % of Cr, with the balance being Fe and unavoidable impurities; a method of producing the same; and a wire material and sheet material composed of the alloy material.
    Type: Application
    Filed: January 18, 2019
    Publication date: May 23, 2019
    Applicants: TOHOKU UNIVERSITY, FURUKAWA TECHNO MATERIAL CO., LTD., FURUKAWA ELECTRIC CO., LTD.
    Inventors: Toshihiro OMORI, Ryosuke KAINUMA, Yuki NOGUCHI, Sumio KISE, Toyonobu TANAKA
  • Publication number: 20190133803
    Abstract: A hallux valgus correction device (1) for correcting hallux valgus, the hallux valgus correction device including: a corrector (10) made of a superelastic alloy; and a fixture (2, 3, and 4) formed from a fabric to attach the corrector, in which the corrector has a hinge part (11) that is rotationally movable in the bending direction and the stretching direction of one toe or a plurality of toes in need of correction.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Applicants: FURUKAWA TECHNO MATERIAL CO., LTD., FURUKAWA ELECTRIC CO., LTD., Tohoku University
    Inventors: Sumio KISE, Toyonobu TANAKA, Ryosuke KAINUMA, Toshihiro OMORI, Masahito HATORI, Tadakuni KAMEDA, Norihito SUZUKI
  • Patent number: 10067005
    Abstract: An apparatus for estimating temperatures of a vehicle includes an acquirer to acquire an engine correlated temperature correlated with the temperature of an engine when the engine is stopping. The apparatus further includes an estimator to estimate a catalyst temperature of a catalyst disposed in an exhaust system of the engine, based on an inlet gas temperature estimated through a first-order lag operation with an exhaust-manifold temperature at a stop of the engine as an initial temperature and the engine correlated temperature as a target temperature.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: September 4, 2018
    Assignee: MITSUBISHI JIDOSHA KOGYO KABUSHIKI KAISHA
    Inventors: Toshiyuki Miyata, Sumio Tanaka
  • Patent number: 9340201
    Abstract: An engine operation control device for a hybrid vehicle, including: an engine provided in a vehicle; a power generator that is driven by the engine to generate electric power; a driving battery that is chargeable with electric power supplied from the power generator; and a front motor and a rear motor that drive wheels with electric power supplied from the driving battery or the power generator, and allowing a series mode in which the front motor drives front wheels and the rear motor drives rear wheels while the engine is operated at a predetermined set rotational speed to drive the power generator to generate electric power, wherein the set rotational speed is set to increase with decreasing of the atmospheric pressure in a present position of the vehicle in the series mode.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: May 17, 2016
    Assignee: MITSUBISHI JIDOSHA KOGYO KABUSHIKI KAISHA
    Inventors: Katsunori Ueda, Sumio Tanaka, Shigetoshi Hirano
  • Publication number: 20150268102
    Abstract: An apparatus for estimating temperatures of a vehicle includes an acquirer to acquire an engine correlated temperature correlated with the temperature of an engine when the engine is stopping. The apparatus further includes an estimator to estimate a catalyst temperature of a catalyst disposed in an exhaust system of the engine, based on an inlet gas temperature estimated through a first-order lag operation with an exhaust-manifold temperature at a stop of the engine as an initial temperature and the engine correlated temperature as a target temperature.
    Type: Application
    Filed: March 19, 2015
    Publication date: September 24, 2015
    Applicant: MITSUBISHI JIDOSHA KOGYO KABUSHIKI KAISHA
    Inventors: Toshiyuki MIYATA, Sumio TANAKA
  • Patent number: 9061683
    Abstract: A traveling mode switching controller of a hybrid electric vehicle has a state-of-charge detection unit; a driver request output detection unit; a correction unit; and a switching control unit for controlling a switch from a first traveling mode to a second traveling mode when a vehicle request output exceeds an output threshold value. In the first traveling mode, an engine is deactivated and the drive motor is activated. In the second traveling mode, drive wheels are actuated by means of driving power of the engine, or a generator connected to the engine is activated to generate electric power to activate the drive motor to actuate the drive wheels. The switching control unit sets the output threshold value low as the state of charge decreases, thereby changing conditions for switching the first traveling mode to the second traveling mode.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: June 23, 2015
    Assignee: MITSUBISHI JIDOSHA KOGYO KABUSHIKI KAISHA
    Inventors: Katsunori Ueda, Sumio Tanaka, Shigetoshi Hirano
  • Publication number: 20140195084
    Abstract: An engine operation control device for a hybrid vehicle, including: an engine provided in a vehicle; a power generator that is driven by the engine to generate electric power; a driving battery that is chargeable with electric power supplied from the power generator; and a front motor and a rear motor that drive drive wheels with electric power supplied from the driving battery or the power generator, and allowing a series mode in which the front motor drives front wheels and the rear motor drives rear wheels while the engine is operated at a predetermined set rotational speed to drive the power generator to generate electric power, wherein the set rotational speed is set to increase with decreasing of the atmospheric pressure in a present position of the vehicle in the series mode.
    Type: Application
    Filed: December 23, 2013
    Publication date: July 10, 2014
    Applicant: Mitsubishi Jidosha Kogyo Kabushiki Kaisha
    Inventors: Katsunori UEDA, Sumio TANAKA, Shigetoshi HIRANO
  • Publication number: 20140180515
    Abstract: A traveling mode switching controller of a hybrid electric vehicle has a state-of-charge detection unit; a driver request output detection unit; a correction unit; and a switching control unit for controlling a switch from a first traveling mode to a second traveling mode when a vehicle request output exceeds an output threshold value. In the first traveling mode, an engine is deactivated and the drive motor is activated. In the second traveling mode, drive wheels are actuated by means of driving power of the engine, or a generator connected to the engine is activated to generate electric power to activate the drive motor to actuate the drive wheels. The switching control unit sets the output threshold value low as the state of charge decreases, thereby changing conditions for switching the first traveling mode to the second traveling mode.
    Type: Application
    Filed: December 20, 2013
    Publication date: June 26, 2014
    Applicant: MITSUBISHI JIDOSHA KOGYO KABUSHIKI KAISHA
    Inventors: Katsunori UEDA, Sumio TANAKA, Shigetoshi HIRANO
  • Publication number: 20080285327
    Abstract: A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
    Type: Application
    Filed: November 2, 2007
    Publication date: November 20, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ryu Ogiwara, Daisaburo Takashima, Sumio Tanaka, Yukihito Oowaki, Yoshiaki Takeuchi
  • Patent number: 7295456
    Abstract: A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
    Type: Grant
    Filed: May 8, 2006
    Date of Patent: November 13, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryu Ogiwara, Daisaburo Takashima, Sumio Tanaka, Yukihito Oowaki, Yoshiaki Takeuchi
  • Publication number: 20060193162
    Abstract: A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
    Type: Application
    Filed: May 8, 2006
    Publication date: August 31, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ryu Ogiwara, Daisaburo Takashima, Sumio Tanaka, Yukihito Oowaki, Yoshiaki Takeuchi
  • Patent number: 7057917
    Abstract: A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
    Type: Grant
    Filed: December 24, 2003
    Date of Patent: June 6, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryu Ogiwara, Daisaburo Takashima, Sumio Tanaka, Yukihito Oowaki, Yoshiaki Takeuchi
  • Publication number: 20040136225
    Abstract: A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
    Type: Application
    Filed: December 24, 2003
    Publication date: July 15, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ryu Ogiwara, Daisaburo Takashima, Sumio Tanaka, Yukihito Oowaki, Yoshiaki Takeuchi
  • Patent number: 6671200
    Abstract: A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
    Type: Grant
    Filed: February 26, 2003
    Date of Patent: December 30, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryu Ogiwara, Daisaburo Takashima, Sumio Tanaka, Yukihito Oowaki, Yoshiaki Takeuchi
  • Publication number: 20030128572
    Abstract: A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
    Type: Application
    Filed: February 26, 2003
    Publication date: July 10, 2003
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ryu Ogiwara, Daisaburo Takashima, Sumio Tanaka, Yukihito Oowaki, Yoshiaki Takeuchi
  • Patent number: 6552922
    Abstract: A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: April 22, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryu Ogiwara, Daisaburo Takashima, Sumio Tanaka, Yukihito Oowaki, Yoshiaki Takeuchi
  • Patent number: 6529414
    Abstract: In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval. With such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.
    Type: Grant
    Filed: October 17, 2001
    Date of Patent: March 4, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeru Atsumi, Sumio Tanaka
  • Publication number: 20020196656
    Abstract: A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
    Type: Application
    Filed: August 27, 2002
    Publication date: December 26, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ryu Ogiwara, Daisaburo Takashima, Sumio Tanaka, Yukihito Oowaki, Yoshiaki Takeuchi
  • Patent number: 6473330
    Abstract: A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
    Type: Grant
    Filed: June 1, 2000
    Date of Patent: October 29, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryu Ogiwara, Daisaburo Takashima, Sumio Tanaka, Yukihito Oowaki, Yoshiaki Takeuchi