Patents by Inventor Sumio Tanaka
Sumio Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20020012273Abstract: In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval. With such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.Type: ApplicationFiled: October 17, 2001Publication date: January 31, 2002Applicant: Kabushiki Kaisha ToshibaInventors: Shigeru Atsumi, Sumio Tanaka
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Patent number: 6324100Abstract: In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval. With such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.Type: GrantFiled: November 9, 2000Date of Patent: November 27, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Shigeru Atsumi, Sumio Tanaka
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Patent number: 6288961Abstract: A semiconductor memory device reads data corresponding to charges stored in a capacitor in a memory cell and rewrites the data. This semiconductor memory device removes charges stored in the capacitor in the memory cell to a bit line or absorbs charges stored in the bit line into the capacitor in the memory cell, thereby generating a potential difference between the bit line pair. This potential difference is sensed by a sense amplifier and rewritten. Before the sense amplifier is operated, the potential difference is generated between the bit line pair. The parasitic capacitances of the bit line pair during operation of the sense amplifier are substantially equalized, and in this state, the potential difference is sensed.Type: GrantFiled: December 10, 1999Date of Patent: September 11, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Sumio Tanaka, Ryu Ogiwara
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Patent number: 6191971Abstract: A ferroelectric memory device includes a plate line driving circuit, dummy plate line driving circuit, constant voltage generator and variable voltage generating circuit. The plate line driving circuit pulse-drives a plate line associated with a memory cell selected at the time of data readout. The dummy plate line driving circuit pulse-drives a dummy plate line associated with a dummy cell connected to a reference bit line which makes a complementary pair with a bit line connected to the selected memory cell. The constant voltage generator generates a voltage which does not depend on an external power supply voltage and the temperature and is kept substantially constant and applies the voltage to the plate line driving circuit as a power supply voltage.Type: GrantFiled: March 16, 1999Date of Patent: February 20, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Sumio Tanaka, Daisaburo Takashima
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Patent number: 6166987Abstract: A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor during an erase mode. The memory device includes a row decoder circuit having an N-channel transistor connected to a word line. The N-channel transistor is provided on a P-type well region of a semiconductor substrate. A negative voltage is applied to the P-type well region during the erase mode, while ground potential is applied thereto during another modes.Type: GrantFiled: November 18, 1999Date of Patent: December 26, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Shigeru Atsumi, Sumio Tanaka
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Patent number: 6151252Abstract: In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval. With such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.Type: GrantFiled: December 21, 1999Date of Patent: November 21, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Shigeru Atsumi, Sumio Tanaka
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Patent number: 6111777Abstract: A dummy cell is provided in every column and consists of a dummy capacitor and two transistors. When the charge of the ferroelectric capacitor is released to one of a bit line pair, a first dummy word line is selected and charge of the dummy capacitor is released to the other of the bit line pair by way of one of the two transistors. When the charge of the ferroelectric capacitor is released to the other of the bit line pair, a second dummy word line is selected and the charge of the dummy capacitor is released to one of the bit line pair by way of the other one of the two transistors. When either one of the first and second dummy word lines is selected the dummy plate driver supplies a clock signal to the dummy capacitor.Type: GrantFiled: September 23, 1999Date of Patent: August 29, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Ryu Ogiwara, Sumio Tanaka
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Patent number: 6097622Abstract: A ferroelectric memory having a memory cell array or a plurality of memory cell arrays, word lines, where each memory cell array includes word lines. The memory also includes a plurality of plate lines, where each memory cell array includes some of the plate lines and the word line corresponds with some of the plate lines, a bit line, a word line select circuit for selecting among the word lines, and plurality of plate line select circuits, where each of the plate line select circuit is coupled to an associated plate line.Type: GrantFiled: June 3, 1997Date of Patent: August 1, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuru Shimizu, Hiroyuki Takenaka, Sumio Tanaka
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Patent number: 6088267Abstract: A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor during an erase mode. The memory device includes a row decoder circuit having an N-channel transistor connected to a word line. The N-channel transistor is provided on a P-type well region of a semiconductor substrate. A negative voltage is applied to the P-type well region during the erase mode, while ground potential is applied thereto during other modes.Type: GrantFiled: January 13, 1998Date of Patent: July 11, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Shigeru Atsumi, Sumio Tanaka
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Patent number: 6061289Abstract: A variable potential generating circuit includes a resistive potential divider circuit and first and second operational amplifiers. The resistive potential divider circuit includes a switching element and a current-scaling type digital/analog converter circuit connected in series between a power supply node and a ground node. The resistive potential divider circuit has a first node at which a divided potential obtained by resistive division of a variable potential to be output from a variable potential output node appears and a second node to which a virtual potential is applied. The first operational amplifier compares the divided potential of the first node with a reference potential to effect the feedback control for setting the variable output potential equal to the reference potential. The second operational amplifier compares the virtual potential of the second node with the reference potential to effect the feedback control for setting the virtual potential equal to the reference potential.Type: GrantFiled: September 28, 1999Date of Patent: May 9, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Yasuo Itoh, Sumio Tanaka
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Patent number: 6046926Abstract: A ferroelectric memory has a memory cell screening test circuit connected to bit lines through switching transistors. In screening, at least one word line is selected, and data is simultaneously written in all memory cells connected to this word line. Since data is not restored after the rewrite, all FRAM cells can be screened under the same condition. By this circuit, a memory cell having a write failure according to the imprint characteristics inherent to the ferroelectric memory is screened.Type: GrantFiled: October 13, 1998Date of Patent: April 4, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Sumio Tanaka, Hiroyuki Takenaka, Mitsuru Shimizu
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Patent number: 6041014Abstract: A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor during an erase mode. The memory device includes a row decoder circuit having an N-channel transistor connected to a word line. The N-channel transistor is provided on a P-type well region of a semiconductor substrate. A negative voltage is applied to the P-type well region during the erase mode, while ground potential is applied thereto during other modes.Type: GrantFiled: May 10, 1999Date of Patent: March 21, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Shigeru Atsumi, Sumio Tanaka
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Patent number: 6023438Abstract: A semiconductor memory device reads data corresponding to charges stored in a capacitor in a memory cell and rewrites the data. This semiconductor memory device removes charges stored in the capacitor in the memory cell to a bit line or absorbs charges stored in the bit line into the capacitor in the memory cell, thereby generating a potential difference between the bit line pair. This potential difference is sensed by a sense amplifier and rewritten. Before the sense amplifier is operated, the potential difference is generated between the bit line pair. The parasitic capacitances of the bit line pair during operation of the sense amplifier are substantially equalized, and in this state, the potential difference is sensed.Type: GrantFiled: November 17, 1998Date of Patent: February 8, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Sumio Tanaka, Ryu Ogiwara
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Patent number: 6011723Abstract: In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval. With such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.Type: GrantFiled: January 11, 1999Date of Patent: January 4, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Shigeru Atsumi, Sumio Tanaka
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Patent number: 6002354Abstract: A variable potential generating circuit includes a resistive potential divider circuit and first and second operational amplifiers. The resistive potential divider circuit includes a switching element and a current-scaling type digital/analog converter circuit connected in series between a power supply node and a ground node. The resistive potential divider circuit has a first node at which a divided potential obtained by resistive division of a variable potential to be output from a variable potential output node appears and a second node to which a virtual potential is applied. The first operational amplifier compares the divided potential of the first node with a reference potential to effect the feedback control for setting the variable output potential equal to the reference potential. The second operational amplifier compares the virtual potential of the second node with the reference potential to effect the feedback control for setting the virtual potential equal to the reference potential.Type: GrantFiled: October 6, 1998Date of Patent: December 14, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Yasuo Itoh, Sumio Tanaka
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Patent number: 5943256Abstract: A nonvolatile ferroelectric memory comprises a memory cell array having memory cells arranged as a matrix array and each including a charge transfer transistor having a source or drain region connected to a bit line and a gate connected to a word line and a ferroelectric capacitor for information storage having one electrode connected to a plate line and the other electrode connected to the drain or source region of the charge transfer transistor. A first dummy line is arranged outside a bit line formed at an end of the memory cell array and second dummy bit lines are arranged between the bit line at the end of the memory cell array and the first dummy bit line. Dummy memory cells are connected to the second dummy bit line and have the same in configuration and size as the memory cells connected to the bit line.Type: GrantFiled: January 2, 1998Date of Patent: August 24, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuru Shimizu, Sumio Tanaka
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Patent number: 5892706Abstract: Circuitry within a ferroelectric memory prevents inversion of the polarization of ferroelectric memory cells caused by a power on reset signal to avoid corruption of data stored therein. A ferroelectric memory includes a memory cell array, a plurality of word lines commonly connected to the gates of the cell transistors in the same row, a plurality of plate lines commonly connected to the plates of the cell capacitors in the same row, a plurality of bit lines commonly connected to one end of the cell transistors in the same row, and a power on reset circuit for generating a power on reset signal of a predetermined level for a predetermined period of time after the power supply is turned on. An erroneous programming prevention circuit within the memory includes a plurality of switching transistors connected between all of the bit lines and plate lines and a plurality of nodes at a predetermined potential.Type: GrantFiled: February 4, 1998Date of Patent: April 6, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuru Shimizu, Sumio Tanaka
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Patent number: 5875129Abstract: In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval. With such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.Type: GrantFiled: November 6, 1996Date of Patent: February 23, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Shigeru Atsumi, Sumio Tanaka
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Patent number: 5812459Abstract: A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor during an erase mode. The memory device includes a row decoder circuit having an N-channel transistor connected to a word line. The N-channel transistor is provided on a P-type well region of a semiconductor substrate. A negative voltage is applied to the P-type well region during the erase mode, while ground potential is applied thereto during other modes.Type: GrantFiled: February 26, 1997Date of Patent: September 22, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Shigeru Atsumi, Sumio Tanaka
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Patent number: 5798964Abstract: Circuitry within a ferroelectric memory prevents inversion of the polarization of ferroelectric memory cells caused by a power on reset signal to avoid corruption of data stored therein. A ferroelectric memory includes a memory cell array, a plurality of word lines commonly connected to the gates of the cell transistors in the same row, a plurality of plate lines commonly connected to the plates of the cell capacitors in the same row, a plurality of bit lines commonly connected to one end of the cell transistors in the same row, and a power on reset circuit for generating a power on reset signal of a predetermined level for a predetermined period of time after the power supply is turned on. An erroneous programming prevention circuit within the memory includes a plurality of switching transistors connected between all of the bit lines and plate lines and a plurality of nodes at a predetermined potential.Type: GrantFiled: August 23, 1995Date of Patent: August 25, 1998Assignee: Toshiba CorporationInventors: Mitsuru Shimizu, Sumio Tanaka