Abstract: In a semiconductor device including graphene, a gate insulating layer may be formed between a gate electrode and a graphene layer, and an interlayer insulating layer may be formed under a portion of the graphene layer under which the gate insulating layer is not formed. The gate insulating layer may include a material that has higher dielectric permittivity than the interlayer insulating layer.

Abstract: A resistive random access memory (RRAM) having a solid solution layer and a method of manufacturing the RRAM are provided. The RRAM includes a lower electrode, a solid solution layer on the lower electrode, a resistive layer on the solid solution layer, and an upper electrode on the resistive layer. The method of manufacturing the RRAM includes forming a lower electrode, forming a solid solution layer on the lower electrode, forming a resistive layer on the solid layer and forming an upper electrode on the resistive layer, wherein the RRAM is formed of a transition metal solid solution.

Abstract: A graphene electronic device includes a multi-layered gate insulating layer between a graphene channel layer and a gate electrode. The multi-layered gate insulating layer includes an organic insulating layer and an inorganic insulating layer on the organic insulating layer.

Abstract: Information storage devices using magnetic domain wall movement, methods of operating the same, and methods of manufacturing the same are provided. An information storage device includes a first magnetic layer, a heating unit and a magnetic field applying unit. The heating unit heats a first region of the first magnetic layer. The magnetic field applying unit applies a magnetic field to the first region to form a magnetic domain. A wall of the magnetic domain is moved by a current applied to the first magnetic layer.

Abstract: An information storage device includes a storage node, a write unit configured to write information to a first magnetic domain region of the storage node, and a read unit configured to read information from a second magnetic domain region of the storage node. The information storage device further includes a temporary storage unit configured to temporarily store information read by the read unit, and a write control unit electrically connected to the temporary storage unit and configured to control current supplied to the write unit. The information read from the second magnetic domain region is stored in the temporary storage unit and written to the first magnetic domain region.

Abstract: Field effect transistors, methods of fabricating a carbon insulating layer using molecular beam epitaxy and methods of fabricating a field effect transistor using the same are provided, the methods of fabricating the carbon insulating layer include maintaining a substrate disposed in a molecular beam epitaxy chamber at a temperature in a range of about 300° C. to about 500° C. and maintaining the chamber in vacuum of 10?11 Torr or less prior to performing an epitaxy process, and supplying a carbon source to the chamber to form a carbon insulating layer on the substrate. The carbon insulating layer is formed of diamond-like carbon and tetrahedral amorphous carbon.

Abstract: The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer.

Abstract: Provided are a field effect transistor, a logic circuit including the same and methods of manufacturing the same. The field effect transistor may include an ambipolar layer that includes a source region, a drain region, and a channel region between the source region and the drain region, wherein the source region, the drain region, and the channel region may be formed in a monolithic structure, a gate electrode on the channel region, and an insulating layer separating the gate electrode from the ambipolar layer, wherein the source region and the drain region have a width greater than that of the channel region in a second direction that crosses a first direction in which the source region and the drain region are connected to each other.

Abstract: Provided may be a semiconductor device using magnetic domain wall movement. The semiconductor device may include a magnetic track having a plurality of magnetic domains and a thermal conductive insulating layer configured to contact the magnetic track. The thermal conductive insulating layer may prevent or reduce the magnetic track from being heated due to a current supplied to the magnetic track.

Abstract: A magnetic structure includes a first portion and a plurality of second portions. The first portion extends in a first direction. The plurality of second portions extend from ends of the first portion in a second direction. The first and second directions are perpendicular to one another. Two magnetic domains magnetized in directions opposite to each other and a magnetic domain wall between the magnetic domains are formed in the magnetic structure.

Abstract: A graphene electronic device includes a graphene channel layer on a substrate, a source electrode on an end portion of the graphene channel layer and a drain electrode on another end portion of the graphene channel layer, a gate oxide on the graphene channel layer and between the source electrode and the drain electrode, and a gate electrode on the gate oxide. The gate oxide has substantially the same shape as the graphene channel layer between the source electrode and the drain electrode.

Abstract: A magnetic memory device includes a lower structure or an antiferromagnetic layer, a pinned layer, an information storage layer, and a free layer formed on the lower structure or the antiferromagnetic layer. In a method of operating a magnetic memory device, information from the storage information layer is read or stored after setting the magnetization of the free layer in a first magnetization direction. The information is stored when the first magnetization direction is opposite to a magnetization direction of the pinned layer, but is read when the first magnetization direction is the same as the magnetization direction of the pinned layer.

Abstract: Graphene electronic devices may include a gate electrode on a substrate, a first gate insulating film covering the gate electrode, a plurality of graphene channel layers on the substrate, a second gate insulating film between the plurality of graphene channel layers, and a source electrode and a drain electrode connected to both edges of each of the plurality of graphene channel layers.

Abstract: The graphene substrate may include a metal oxide film on a substrate, and a graphene layer on the metal oxide film. The concentration of oxygen in the metal oxide film may be gradually reduced from the substrate towards the graphene layer, and the graphene layer may be formed directly on the metal oxide film.

Abstract: A graphene electronic device includes a gate electrode, a gate oxide disposed on the gate electrode, a graphene channel layer formed on the gate oxide, and a source electrode and a drain electrode respectively disposed on both ends of the graphene channel layer. In the graphene channel layer, a plurality of nanoholes are arranged in a single line in a width direction of the graphene channel layer.

Abstract: In a semiconductor device including graphene, a gate insulating layer may be formed between a gate electrode and a graphene layer, and an interlayer insulating layer may be formed under a portion of the graphene layer under which the gate insulating layer is not formed. The gate insulating layer may include a material that has higher dielectric permittivity than the interlayer insulating layer.

Abstract: A nonvolatile memory device including one transistor and one resistant material and a method of manufacturing the nonvolatile memory device are provided. The nonvolatile memory device includes a substrate, a transistor formed on the substrate, and a data storage unit connected to a drain of the transistor. The data storage unit includes a data storage material layer having different resistance characteristics in different voltage ranges.

Abstract: A method of analyzing single thread access by a variable of a multi-threaded program is provided. The method includes computing a thread identifier of a thread to be executed in a node of the multi-thread program; computing multiple threads configured to concurrently execute the node; and computing thread accessibility by deducing one or more variables that are executed in a single thread of the program from one or more pairs of the computed threads that concurrently execute the node.

Abstract: Provided are a stack structure including an epitaxial graphene, a method of forming the stack structure, and an electronic device including the stack structure. The stack structure includes: a Si substrate; an under layer formed on the Si substrate; and at least one epitaxial graphene layer formed on the under layer.

Abstract: A graphene electronic device and a method of fabricating the graphene electronic device are provided. The graphene electronic device may include a graphene channel layer formed on a hydrophobic polymer layer, and a passivation layer formed on the graphene channel layer. The hydrophobic polymer layer may prevent or reduce adsorption of impurities to transferred graphene, and a passivation layer may also prevent or reduce adsorption of impurities to a heat-treated graphene channel layer.