Abstract: Provided is an instrumentation apparatus and method for inserting an instrumentation function into a program. The instrumentation function may be inserted into code that is outside of a loop of a program or a system library function relevant to the program.

Abstract: The graphene device may include an upper oxide layer on at least one embedded gate, and a graphene channel and a plurality of electrodes on the upper oxide layer. The at least one embedded gate may be formed on the substrate. The graphene channel may be formed on the plurality of electrodes, or the plurality of electrodes may be formed on the graphene channel.

Abstract: An information storage device includes a memory region having a magnetic track and a write/read unit, and a control circuit connected to the memory region. First and second switching devices are connected to both ends of the magnetic track, and a third switching device is connected to the write/read unit. The control circuit controls the first to third switching devices, and supplies operating current to at least one of the magnetic track and the write/read unit.

Abstract: Provided is a method of operating a magnetic random access memory device comprising a switch structure and a magnetoresistance structure. According to the method, current variation depending on the direction of the current can be reduced by controlling a gate voltage of the switch structure when supplying current to write data to the magnetoresistance structure.

Abstract: Oscillators and methods of manufacturing and operating the same are provided, the oscillators include a pinned layer, a free layer and a barrier layer having at least one filament between the pinned layer and the free layer. The pinned layer may have a fixed magnetization direction. The free layer corresponding to the pinned layer. The at least one filament in the barrier layer may be formed by applying a voltage between the pinned layer and the free layer. The oscillators may be operated by inducing precession of a magnetic moment of at least one region of the free layer that corresponds to the at least one filament, and detecting a resistance change of the oscillator due to the precession.

Abstract: Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous.

Abstract: An oscillator and a method of operating the same are provided, the oscillator may include a free layer, a pinned layer on a first surface of the free layer, and a reference layer on a second surface of the free layer. The free layer may have a variable magnetization direction. The pinned layer may have a pinned magnetization direction. The reference layer may have a magnetization direction non-parallel to the magnetization direction of the pinned layer.

Abstract: Provided are information storage devices using movement of magnetic domain walls and methods of operating information storage devices. An information storage device includes a magnetic track and an operating unit. The magnetic track includes a plurality of magnetic domains separated by magnetic domain walls. The size of the operating unit is sufficient to cover at least two adjacent magnetic domains. And, the operating unit may be configured to write/read information to/from a single magnetic domain as well as a plurality of magnetic domains of the magnetic track.

Abstract: Oscillators and method of operating the same are provided, the oscillators include a magnetic layer, and a magnetization fixing element configured to fix a magnetization direction of the magnetic layer. The oscillators generate a signal by using precession of a magnetic moment of the magnetic layer.

Abstract: Field effect transistors, methods of fabricating a carbon insulating layer using molecular beam epitaxy and methods of fabricating a field effect transistor using the same are provided, the methods of fabricating the carbon insulating layer include maintaining a substrate disposed in a molecular beam epitaxy chamber at a temperature in a range of about 300° C. to about 500° C. and maintaining the chamber in vacuum of 10?11 Torr or less prior to performing an epitaxy process, and supplying a carbon source to the chamber to form a carbon insulating layer on the substrate. The carbon insulating layer is formed of diamond-like carbon and tetrahedral amorphous carbon.

Abstract: Oscillators and methods of operating the same, the oscillators include a pinned layer having a fixed magnetization direction, a first free layer over the pinned layer, and a second free layer over the first free layer. The oscillators are configured to generate a signal using precession of a magnetic moment of at least one of the first and second free layers.

Abstract: A nonvolatile memory device including one transistor and one resistant material and a method of manufacturing the nonvolatile memory device are provided. The nonvolatile memory device includes a substrate, a transistor formed on the substrate, and a data storage unit connected to a drain of the transistor. The data storage unit includes a data storage material layer having different resistance characteristics in different voltage ranges.

Abstract: Provided is a graphene device and a method of manufacturing the same. The graphene device may include an upper oxide layer on at least one embedded gate, and a graphene channel and a plurality of electrodes on the upper oxide layer. The at least one embedded gate may be formed on the substrate. The graphene channel may be formed on the plurality of electrodes, or the plurality of electrodes may be formed on the graphene channel.

Abstract: A memory cell includes: a memory cell array unit having a plurality of nano wires arranged vertically on a substrate, each of the plurality of nano wires having a plurality of domains for storing information; a nano wire selection unit formed on the substrate and configured to select at least one of the plurality of nano wires; a domain movement control unit formed on the substrate and configured to control a domain movement operation with respect to at least one of the plurality of nano wires; and a read/write control unit formed on the substrate and configured to control at least one of a read operation and a write operation with respect to at least one of the plurality of nano wires.

Abstract: Field effect transistors, methods of fabricating a carbon insulating layer using molecular beam epitaxy and methods of fabricating a field effect transistor using the same are provided, the methods of fabricating the carbon insulating layer include maintaining a substrate disposed in a molecular beam epitaxy chamber at a temperature in a range of about 300° C. to about 500° C. and maintaining the chamber in vacuum of 10?11 Torr or less prior to performing an epitaxy process, and supplying a carbon source to the chamber to form a carbon insulating layer on the substrate. The carbon insulating layer is formed of diamond-like carbon and tetrahedral amorphous carbon.

Abstract: Graphene, a method of fabricating the same, and a transistor having the graphene are provided, the graphene includes a structure of carbon (C) atoms partially substituted with boron (B) atoms and nitrogen (N) atoms. The graphene has a band gap. The graphene substituted with boron and nitrogen may be used as a channel of a field effect transistor. The graphene may be formed by performing chemical vapor deposition (CVD) method using borazine or ammonia borane as a boron nitride (B—N) precursor.

Abstract: An information storage device includes a magnetic structure having a buffer track and a plurality of storage tracks connected to the buffer track. A write/read unit is disposed on the magnetic structure, and a plurality of switching devices are respectively connected to the buffer track, the plurality of storage tracks, and the write/read unit. The switching devices that are respectively connected to the buffer track and the storage tracks. The information storage device further includes a circuit configured to supply current to at least one of the magnetic structure and the write/read unit.

Abstract: An apparatus and method for optimizing an application to be executed in an execution environment of a client are provided. For example, on-demand optimizing of the performance of applications may be performed such that the applications are suitable for execution environments of various types of Consumer Electronic (CE) equipment, in order to distribute high performance applications.

Abstract: A magnetic track includes first and second magnetic domain regions having different lengths and different magnetic domain wall movement speeds. A longer of the first and second magnetic domain regions serves as an information read/write region. An information storage device includes a magnetic track. The magnetic track includes a plurality of magnetic domain regions and a magnetic domain wall region formed between neighboring magnetic domain regions. The plurality of magnetic domain regions includes a first magnetic domain region and at least one second magnetic domain region having a smaller length than the first magnetic domain region. The information storage device further includes a first unit configured to perform at least one of an information recording operation and an information reproducing operation on the first magnetic domain region, and a magnetic domain wall movement unit configured to move a magnetic domain wall of the magnetic domain wall region.

Abstract: A graphene electronic device may include a silicon substrate, connecting lines on the silicon substrate, a first electrode and a second electrode on the silicon substrate, and an interlayer dielectric on the silicon substrate. The interlayer dielectric may be configured to cover the connecting lines and the first and second electrodes and the interlayer dielectric may be further configured to expose at least a portion of the first and second electrodes. The graphene electronic device may further include an insulating layer on the interlayer dielectric and a graphene layer on the insulating layer, the graphene layer having a first end and a second end. The first end of the graphene layer may be connected to the first electrode and the second end of the graphene layer may be connected to the second electrode.