Patents by Inventor Sun-ae Seo

Sun-ae Seo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Nonvolatile memory device including nano dot and method of fabricating the same
    Patent number: 7998804
    Abstract: A nonvolatile memory device including a nano dot and a method of fabricating the same are provided. The nonvolatile memory device may include a lower electrode, an oxide layer on the lower electrode, a nano dot in the oxide layer and an upper electrode on the oxide layer. In example embodiments, the current paths inside the oxide layer may be unified, thereby stabilizing the reset current.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: August 16, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jin Park, Myoung-Jae Lee, Young-Kwan Cha, Sun-Ae Seo, Kyung-Sang Cho, Kwang-Soo Seol
  • Cross-point latch and method of operating the same
    Patent number: 7994815
    Abstract: Provided is a cross-point latch and a method of operating the cross-point latch. The cross-point latch includes a signal line, two control lines crossing the signal line, and unipolar switches disposed at crossing points between the signal line and the control lines.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: August 9, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-jong Chung, Sun-ae Seo, Chang-won Lee, Dae-young Jeon, Ran-ju Jung, Dong-chul Kim, Ji-young Bae
  • Quantum interference transistors and methods of manufacturing and operating the same
    Patent number: 7978006
    Abstract: A quantum interference transistor may include a source; a drain; N channels (N?2), between the source and the drain, and having N?1 path differences between the source and the drain; and at least one gate disposed at one or more of the N channels. One or more of the N channels may be formed in a graphene sheet. A method of manufacturing the quantum interference transistor may include forming one or more of the N channels using a graphene sheet. A method of operating the quantum interference transistor may include applying a voltage to the at least one gate. The voltage may shift a phase of a wave of electrons passing through a channel at which the at least one gate is disposed.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: July 12, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jai-kwang Shin, Sun-ae Seo, Jong-seob Kim, Ki-ha Hong, Hyun-jong Chung
  • Perpendicular magnetic tunnel junctions, magnetic devices including the same and method of manufacturing a perpendicular magnetic tunnel junction
    Publication number: 20110149647
    Abstract: Provided are a perpendicular magnetic tunnel junction (MTJ), a magnetic device including the same, and a method of manufacturing the MTJ, the perpendicular MTJ includes a lower magnetic layer; a tunnelling layer on the lower magnetic layer; and an upper magnetic layer on the tunnelling layer. One of the upper and lower magnetic layers includes a free magnetic layer that exhibits perpendicular magnetic anisotropy, wherein the magnetizing direction of the free magnetic layer is changed by a spin polarization current. A polarization enhancing layer (PEL) and an exchange blocking layer (EBL) are stacked between the tunnelling layer and the free magnetic layer.
    Type: Application
    Filed: November 18, 2010
    Publication date: June 23, 2011
    Inventors: Kwang-seok Kim, Taek-dong Lee, Woo-jin Kim, Sun-ae Seo, Kee-won Kim, Sun-ok Kim
  • Spin valve device including graphene, method of manufacturing the same, and magnetic device including the spin valve device
    Publication number: 20110149670
    Abstract: Provided are a spin valve device including graphene, a method of manufacturing the spin valve device, and a magnetic device including the spin valve device. The spin valve device may include at least one of a graphene sheet or a hexagonal boron nitride (h-BN) sheet between a lower magnetic layer and an upper magnetic layer. The graphene sheet may have a single layer structure or a multilayer structure. The spin valve device may further include a spacer between the lower magnetic layer and the graphene sheet. The spin valve device may further include a spacer between the graphene sheet and the upper magnetic layer.
    Type: Application
    Filed: August 24, 2010
    Publication date: June 23, 2011
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jin-seong Heo, Sun-ae Seo, Yun-sung Woo, Hyun-jong Chung
  • Magnetic tunnel junction devices, electronic devices including a magnetic tunneling junction device and methods of fabricating the same
    Publication number: 20110141803
    Abstract: Perpendicular magnetic tunnel junction (MTJ) devices, methods of fabricating a perpendicular MTJ device, electronic devices including a perpendicular MTJ device and methods of fabricating the electronic device are provided, the perpendicular MTJ devices include a pinned layer, a tunneling layer and a free layer. At least one of the pinned layer and the free layer includes a multi-layered structure including an amorphous perpendicular magnetic anisotropy (PMA) material.
    Type: Application
    Filed: September 17, 2010
    Publication date: June 16, 2011
    Applicants: Samsung Electronics Co., Ltd., Gwangju Institute of Science and Technology
    Inventors: Kwang-seok Kim, Kee-won Kim, Sun-ae Seo, Seung-kyo Lee, Young-man Jang
  • Non-volatile logic circuits, integrated circuits including the non-volatile logic circuits, and methods of operating the integrated circuits
    Patent number: 7961005
    Abstract: Provided is a non-volatile logic circuit that includes a latch unit having a pair of latch nodes and a pair of non-volatile memory cells to be supplied first and second write voltages according to data of the pair of latch nodes when a write enable signal is activated such that a write operation is performed with respect to the pair of non-volatile memory cells. The first and second write voltages are different and logic values of data written to the respective non-volatile memory cells are different.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: June 14, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-jung Kim, Jae-kwang Shin, Sun-ae Seo
  • NON-VOLATILE LOGIC CIRCUITS, INTEGRATED CIRCUITS INCLUDING THE NON-VOLATILE LOGIC CIRCUITS, AND METHODS OF OPERATING THE INTEGRATED CIRCUITS
    Publication number: 20110133778
    Abstract: Provided is a non-volatile logic circuit that includes a latch unit having a pair of latch nodes and a pair of non-volatile memory cells to be supplied first and second write voltages according to data of the pair of latch nodes when a write enable signal is activated such that a write operation is performed with respect to the pair of non-volatile memory cells. The first and second write voltages are different and logic values of data written to the respective non-volatile memory cells are different.
    Type: Application
    Filed: August 5, 2010
    Publication date: June 9, 2011
    Inventors: Ho-jung KIM, Jae-kwang SHIN, Sun-ae SEO
  • Field effect transistors, methods of fabricating a carbon-insulating layer using molecular beam epitaxy and methods of fabricating a field effect transistor
    Publication number: 20110121409
    Abstract: Field effect transistors, methods of fabricating a carbon insulating layer using molecular beam epitaxy and methods of fabricating a field effect transistor using the same are provided, the methods of fabricating the carbon insulating layer include maintaining a substrate disposed in a molecular beam epitaxy chamber at a temperature in a range of about 300° C. to about 500° C. and maintaining the chamber in vacuum of 10?11 Torr or less prior to performing an epitaxy process, and supplying a carbon source to the chamber to form a carbon insulating layer on the substrate. The carbon insulating layer is formed of diamond-like carbon and tetrahedral amorphous carbon.
    Type: Application
    Filed: September 10, 2010
    Publication date: May 26, 2011
    Inventors: David Seo, Jai-kwang Shin, Sun-ae Seo
  • Methods of fabricating graphene using alloy catalyst
    Publication number: 20110108609
    Abstract: Methods of fabricating graphene using an alloy catalyst may include forming an alloy catalyst layer including nickel on a substrate and forming a graphene layer by supplying hydrocarbon gas onto the alloy catalyst layer. The alloy catalyst layer may include nickel and at least one selected from the group consisting of copper, platinum, iron and gold. When the graphene is fabricated, a catalyst metal that reduces solubility of carbon in Ni may be used together with Ni in the alloy catalyst layer. An amount of carbon that is dissolved may be adjusted and a uniform graphene monolayer may be fabricated.
    Type: Application
    Filed: July 12, 2010
    Publication date: May 12, 2011
    Inventors: Yun-sung Woo, David Seo, Sun-ae Seo, Hyun-jong Chung, Sae-ra Kang, Jin-seong Heo
  • Methods of manufacturing and transferring larger-sized graphene
    Publication number: 20110108521
    Abstract: Example embodiments relate to methods of manufacturing and transferring a larger-sized graphene layer. A method of transferring a larger-sized graphene layer may include forming a graphene layer, a protection layer, and an adhesive layer on a substrate and removing the substrate. The graphene layer may be disposed on a transferring substrate by sliding the graphene layer onto the transferring substrate.
    Type: Application
    Filed: September 21, 2010
    Publication date: May 12, 2011
    Inventors: Yun-sung Woo, David Seo, Su-kang Bae, Sun-ae Seo, Hyun-jong Chung, Sae-ra Kang, Jin-seong Heo, Myung-hee Jung
  • APPARATUS AND METHOD FOR EXECUTING AN APPLICATION
    Publication number: 20110106916
    Abstract: Provided are an apparatus and method for executing an application. Using the apparatus and method, an application is executed in a terminal directly, or by receiving a computing service from a remote server. After an execution time and/or power consumption of when the application is executed in the terminal directly, and an execution time and/or power consumption when the computing service is received from the remote server are estimated, one of the application execution methods of the two cases may be selected according to the estimated values. The estimated values may be determined based on a state of the terminal, the quality of service (QoS) state of the remote server, and a characteristic of the application.
    Type: Application
    Filed: July 29, 2010
    Publication date: May 5, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-Hyun CHO, Sung-Do MOON, Byung-Chang CHA, Sun-Ae SEO
  • Non-volatile memory devices and methods of fabricating the same
    Patent number: 7936044
    Abstract: A memory device may include a switching device and a storage node coupled with the switching device. The storage node may include a first electrode, a second electrode, a data storage layer and at least one contact layer. The data storage layer may be disposed between the first electrode and the second electrode and may include a transition metal oxide or aluminum oxide. The at least one contact layer may be disposed at least one of above or below the data storage layer and may include a conductive metal oxide.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: May 3, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Chul Kim, In-kyeong Yoo, Myoung-jae Lee, Sun-ae Seo, In-gyu Baek, Seung-eon Ahn, Byoung-ho Park, Young-kwan Cha, Sang-jin Park
  • Nonvolatile memory device, array of nonvolatile memory devices, and methods of making the same
    Patent number: 7935953
    Abstract: A nonvolatile memory device including a lower electrode, a resistor structure disposed on the lower electrode, a middle electrode disposed on the resistor structure, a diode structure disposed on the middle electrode, and an upper electrode disposed on the diode structure. A nonvolatile memory device wherein the resistor structure includes one resistor and the diode structure includes one diode. An array of nonvolatile memory device as described above. Methods of manufacturing a nonvolatile memory device and an array of nonvolatile memory device.
    Type: Grant
    Filed: November 2, 2007
    Date of Patent: May 3, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Eon Ahn, In-Kyeong Yoo, Young-Soo Joung, Young-Kwan Cha, Myoung-Jae Lee, David Seo, Sun-Ae Seo
  • Methods for fixing graphene defects using a laser beam and methods of manufacturing an electronic device
    Publication number: 20110092054
    Abstract: Methods of fixing graphene using a laser beam and methods of manufacturing an electronic device are provided, the method of fixing graphene includes fixing a defect of a graphene nanoribbon by irradiating the laser beam onto the graphene nanoribbon.
    Type: Application
    Filed: August 27, 2010
    Publication date: April 21, 2011
    Inventors: Sun-ae Seo, Dong-chul Kim, Yun-sung Woo, Hyun-jong Chung, Jin-seong Heo
  • Electronic device using a two-dimensional sheet material, transparent display and methods of fabricating the same
    Publication number: 20110089403
    Abstract: An electronic device, a transparent display and methods for fabricating the same are provided, the electronic device including a first, a second and a third element each formed of a two-dimensional (2D) sheet material. The first, second, and third elements are stacked in a sequential order or in a reverse order. The second element is positioned between the first element and the third element. The second element has an insulator property, the first and third elements have a metal property or a semiconductor property.
    Type: Application
    Filed: September 7, 2010
    Publication date: April 21, 2011
    Inventors: Yun-sung Woo, Sun-ae Seo, Dong-chul Kim, Hyun-jong Chung
  • Graphene device and method of manufacturing the same
    Publication number: 20110089995
    Abstract: Provided is a graphene device and a method of manufacturing the same. The graphene device may include an upper oxide layer on at least one embedded gate, and a graphene channel and a plurality of electrodes on the upper oxide layer. The at least one embedded gate may be formed on the substrate. The graphene channel may be formed on the plurality of electrodes, or the plurality of electrodes may be formed on the graphene channel.
    Type: Application
    Filed: August 25, 2010
    Publication date: April 21, 2011
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jin seong Heo, Sun-ae Seo, Dong-chul Kim, Yun-sung Woo, Hyun-jong Chung
  • Magneto-resistive devices, information storage devices including the same and methods of operating information storage devices
    Publication number: 20110085258
    Abstract: An information storage device includes a magnetic track and a magnetic domain wall moving unit. The magnetic track has a plurality of magnetic domains and a magnetic domain wall between each pair of adjacent magnetic domains. The magnetic domain wall moving unit is configured to move at least the magnetic domain wall. The information storage device further includes a magneto-resistive device configured to read information recorded on the magnetic track. The magneto-resistive device includes a pinned layer, a free layer and a separation layer arranged there between. The pinned layer has a fixed magnetization direction. The free layer is disposed between the pinned layer and the magnetic track, and has a magnetization easy axis, which is non-parallel to the magnetization direction of the pinned layer.
    Type: Application
    Filed: June 22, 2010
    Publication date: April 14, 2011
    Inventors: Ji-young Bae, Sung-chul Lee, Sun-ae Seo, Young-jin Cho, Ung-hwan Pi, Jin-seong Heo
  • Information storage devices and methods of operating the same
    Patent number: 7924593
    Abstract: Provided are an information storage device and a method of operating the same. The information storage device includes: a magnetic layer having a plurality of magnetic domain regions and a magnetic domain wall interposed between the magnetic domain regions; a first unit disposed on a first region which is one of the plurality of magnetic domain regions for recording information to the first region; a second unit connected to the first unit for inducing a magnetic field so as to record information to the first region.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: April 12, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-chul Lee, Sun-ae Seo, Young-jin Cho, Ung-hwan Pi, Ji-young Bae
  • Oscillators and methods of operating the same
    Publication number: 20110080221
    Abstract: An oscillator includes: a plurality of free layers and a non-magnetic layer disposed between the plurality of free layers. Each of the plurality of free layers has perpendicular magnetic anisotropy or in-plane magnetic anisotropy. Magnetization directions of the free layers are periodically switched such that a signal within a given frequency band oscillates.
    Type: Application
    Filed: June 22, 2010
    Publication date: April 7, 2011
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sung-chul Lee, Sun-ae Seo, Young-jin Cho, Ung-hwan Pi, Kwang-seok Kim, Ji-young Bae