Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device may be a complementary device including a p-type oxide TFT and an n-type oxide TFT. The semiconductor device may be a logic device such as an inverter, a NAND device, or a NOR device.

Abstract: A method of aging a field emission device including a cathode and an anode arranged parallel to each other, an emitter arranged on the cathode to emit electrons to the anode, and a gate electrode arranged on the cathode adjacent to the emitter, the method including: supplying a voltage to the cathode; supplying a voltage to the gate; and then supplying a sufficiently low voltage to the anode so as to prevent a short-circuited portion between the cathode and the gate electrode from being permanently damaged due to an overcurrent.

Abstract: The inverter includes a driving transistor and a loading transistor having channel regions with different thicknesses. The channel region of the driving transistor may be thinner than the channel region of the load transistor. A channel layer of the driving transistor may have a recessed region between a source and a drain which contact both ends of the channel layer. The driving transistor may be an enhancement mode transistor and the load transistor may be a depletion mode transistor.

Abstract: Electrostatic chucks and methods of manufacturing the same are provided herein. In some embodiments, an electrostatic chuck comprises an electrically conductive body having one or more channels formed in an upper surface thereof; a plate positioned within the one or more channels to define one or more plenums between the body and the plate, wherein the surfaces of the plenum are anodized; one or more fluid passages disposed in the plate and fluidly coupling the one or more plenums to the upper surface of the body, wherein the surfaces of the fluid passages are electrically insulated; and a dielectric layer disposed over the upper surface of the body and the plate, wherein the dielectric layer forms a support surface for a substrate to be disposed thereon.

Abstract: Provided is a multi-layered memory apparatus including an oxide thin film transistor. The multi-layered memory apparatus includes an active circuit unit and a memory unit formed on the active circuit unit. A row line and a column line are formed on memory layers. A selection transistor is formed at a side end of the row line and the column line.

Abstract: A stacked memory device includes a plurality of memory layers, where at least one of the plurality of memory layers is stacked on another of the plurality of memory layers and each of the memory layers includes an array of memory cells, a first active circuit unit configured to classify and process address information for at least one of the memory cells as vertical address information and horizontal address information, and at least one second active circuit unit configured to generate a memory selection signal for at least one of the memory cells based on signals processed by the first active circuit unit.

Abstract: An apparatus and method for calculating life expectancy in mobile communication terminal are provided that include inputting user data when a life expectancy program menu is selected, calculating the life expectancy using the inputted user data, and displaying a calculated result on a display unit.

Abstract: Channel layers and semiconductor devices including the channel layers are disclosed. A channel layer may include a multi-layered structure. Layers forming the channel layer may have different carrier mobilities and/or carrier densities. The channel layer may have a double layered structure including a first layer and a second layer which may be formed of different oxides. Characteristics of the transistor may vary according to materials used to form the channel layers and/or thicknesses thereof.

Abstract: Provided are oxide semiconductors and thin film transistors of the same. An oxide semiconductor includes Zn, In and Hf. The amount of Hf is in the range of about 2-16 at %, inclusive, based on the total amount of Zn, In, and Hf. A thin film transistor includes a gate and a gate insulating layer arranged on the gate. A channel corresponding to the gate is formed on the gate insulating layer. The channel includes an oxide semiconductor. The semiconductor oxide includes Zn, In and Hf. The amount of Hf is in the range of about 2-16 at %, inclusive, based on the total amount of Zn, In, and Hf. A source and a drain contact respective sides of the channel.

Abstract: An electron beam focusing electrode and an electron gun using the same may include a plate having a polygonal through-hole; at least a projecting portion formed on at least one side of the through-hole. By using the electron beam focusing electrode, a spreading phenomenon of an electron beam having a rectangular cross section may be reduced. Further, the output of the electron gun may be increased, and electron beams may be easily focused.

Abstract: A transistor according to example embodiments may include a channel layer, a source and a drain respectively contacting ends of the channel layer, a gate electrode separated from the channel layer, a gate insulating layer interposed between the channel layer and the gate electrode, and/or an insertion layer that is formed between the channel layer and the gate insulating layer. The insertion layer may have a work function different from that of the channel layer.

Abstract: A method of multi-stage substrate etching is provided.

Abstract: A thin-film transistor (TFT) substrate includes a semiconductor pattern, a conductive pattern, a first wiring pattern, an insulation pattern and a second wiring pattern. The semiconductor pattern is formed on a substrate. The conductive pattern is formed as a layer identical to the semiconductor pattern on the substrate. The first wiring pattern is formed on the semiconductor pattern. The first wiring pattern includes a source electrode and a drain electrode spaced apart from the source electrode. The insulation pattern is formed on the substrate having the first wiring pattern to cover the first wiring pattern. The second wiring pattern is formed on the insulation pattern. The second wiring pattern includes a gate electrode formed on the source and drain electrodes. Therefore, a TFT substrate is manufactured using two or three masks, so that manufacturing costs may be decreased.

Abstract: An oxide thin film transistor and a method of manufacturing the oxide TFT are provided. The oxide thin film transistor (TFT) including: a gate; a channel formed to correspond to the gate, and a capping layer having a higher work function than the channel; a gate insulator disposed between the gate and the channel; and a source and drain respectively contacting either side of the capping layer and the channel and partially on a top surface of the capping layer.

Abstract: Example embodiments provide a nonvolatile memory device that may be integrated through stacking, a stack module, and a method of fabricating the nonvolatile memory device. In the nonvolatile memory device according to example embodiments, at least one bottom gate electrode may be formed on a substrate. At least one charge storage layer may be formed on the at least one bottom gate electrode, and at least one semiconductor channel layer may be formed on the at least one charge storage layer.

Abstract: A method of multi-stage substrate etching and a terahertz oscillator manufactured by using the method are provided. The method comprises the steps of forming a first mask pattern on any one surface of a first substrate, forming a hole by etching the first substrate using the first mask pattern as an etching mask, bonding, to the first substrate, a second substrate having the same thickness as a depth to be etched, forming a second mask pattern on the second substrate bonded, forming a hole by etching the second substrate using the second mask pattern as an etching mask, and removing an oxide layer having the etching selectivity between the first substrate and the second substrate, whereby the etched bottom is made uniformly even in a deep step, the edge curvature is minimized, and a T-shape is prevented from being formed on the etched wall face to thereby improve the etching quality.

Abstract: Provided is a channel layer for a thin film transistor, a thin film transistor and methods of forming the same. A channel layer for a thin film transistor may include IZO (indium zinc oxide) doped with a transition metal. A thin film transistor may include a gate electrode and the channel layer formed on a substrate, a gate insulating layer formed between the gate electrode and channel layer, and a source electrode and a drain electrode which contact ends of the channel layer.

Abstract: A nonvolatile semiconductor device according to example embodiments may include a plurality of memory cells on a semiconductor substrate and at least one selection transistor on the semiconductor substrate, wherein the at least one selection transistor may be disposed at a different level from the plurality of memory cells. The at least one selection transistor may be connected to a data line and/or a power source line via a first contact and/or a third contact, respectively. The at least one selection transistor may be connected to the plurality of memory cells via a second contact and/or a fourth contact. The active layer of the at least one selection transistor may contain an oxide. Accordingly, the nonvolatile semiconductor device according to example embodiments may include a selection transistor having a reduced size.

Abstract: Oxide semiconductors and thin film transistors (TFTs) including the same are provided. An oxide semiconductor includes Zn atoms and at least one of Ta and Y atoms added thereto. A thin film transistor (TFT) includes a channel including an oxide semiconductor including Zn atoms and at least one of Ta and Y atoms added thereto.

Abstract: A nano-resonator including a beam having a composite structure may include a silicon carbide beam and/or a metal conductor. The metal conductor may be vapor-deposited on the silicon carbide beam. The metal conductor may have a density lower than a density of the silicon carbide beam.