Abstract: A method includes bonding an electronic die to a photonic die. The photonic die includes an opening. The method further includes attaching an adapter onto the photonic die, with a portion of the adapter being at a same level as a portion of the electronic die, forming a through-hole penetrating through the adapter, with the through-hole being aligned to the opening, and attaching an optical device to the adapter. The optical device is configured to emit a light into the photonic die or receive a light from the photonic die.

Abstract: A method includes bonding an electronic die to a photonic die. The photonic die includes an opening. The method further includes attaching an adapter onto the photonic die, with a portion of the adapter being at a same level as a portion of the electronic die, forming a through-hole penetrating through the adapter, with the through-hole being aligned to the opening, and attaching an optical device to the adapter. The optical device is configured to emit a light into the photonic die or receive a light from the photonic die.

Abstract: A semiconductor device includes an electronic component, a package, a substrate and a plurality of first conductors and second conductors. The package is over the electronic component. T substrate is between the electronic component and the package. The substrate includes a first portion covered by the package, and a second portion protruding out of an edge of the package and uncovered by the package. The first conductors and second conductors are between and electrically connected to the electronic component and the substrate. A width of a second conductor of the plurality of second conductors is larger than a width of a first conductor of the plurality of first conductors, the first conductors are disposed between the second portion of the substrate and the electronic component, and the second conductors are disposed between the first portion of the substrate and the electronic component.

Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

Abstract: A semiconductor device includes a substrate, a package, first conductors and second conductors. The substrate includes a first surface and a second surface opposite to the first surface. The package is disposed over the substrate. The first conductors are disposed over the substrate. The second conductors are disposed over the substrate, wherein the first conductors and the second conductors are substantially at a same tier, and a width of the second conductor is larger than a width of the first conductor.

Abstract: A three-dimensional chip stack includes a first chip bonded to a second chip to form an electrical interconnection therebetween. The bonded interconnection includes a first conductive pillar overlying a first substrate of the first chip, a second conductive pillar overlying a second substrate of the second chip, and a joint structure between the first conductive pillar and the second conductive pillar. The joint structure includes a first IMC region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region.

Abstract: A method includes bonding an electronic die to a photonic die. The photonic die includes an opening. The method further includes attaching an adapter onto the photonic die, with a portion of the adapter being at a same level as a portion of the electronic die, forming a through-hole penetrating through the adapter, with the through-hole being aligned to the opening, and attaching an optical device to the adapter. The optical device is configured to emit a light into the photonic die or receive a light from the photonic die.

Abstract: An embodiment method includes bonding a first die to a first side of an interposer, the interposer comprising a substrate; after bonding the first die to the first side of the interposer, depositing a first insulating layer on a second side of the interposer opposite the first side; patterning an opening through the substrate and the first insulating layer; and depositing a second insulating layer over the first insulating layer and along sidewalls and a lateral surface of the opening. The second insulating layer comprises silicon. The method further includes removing lateral portions of the second insulating layer to define a sidewall spacer on sidewalls of the opening and forming a through via in the opening, wherein the through via is electrically connected to the first die.

Abstract: A semiconductor device includes a substrate, a package, first conductors and second conductors. The substrate includes a first surface and a second surface opposite to the first surface. The package is disposed over the substrate. The first conductors are disposed over the substrate. The second conductors are disposed over the substrate, wherein the first conductors and the second conductors are substantially at a same tier, and a width of the second conductor is larger than a width of the first conductor.

Abstract: In order to prevent cracks from occurring at the corners of semiconductor dies after the semiconductor dies have been bonded to other substrates, an opening is formed adjacent to the corners of the semiconductor dies, and the openings are filled and overfilled with a buffer material that has physical properties that are between the physical properties of the semiconductor die and an underfill material that is placed adjacent to the buffer material.

Abstract: A method includes bonding an electronic die to a photonic die. The photonic die includes an opening. The method further includes attaching an adapter onto the photonic die, with a portion of the adapter being at a same level as a portion of the electronic die, forming a through-hole penetrating through the adapter, with the through-hole being aligned to the opening, and attaching an optical device to the adapter. The optical device is configured to emit a light into the photonic die or receive a light from the photonic die.

Abstract: A package includes a package component, a device die over and bonded to the package component, a metal cap having a top portion over the device die, and a thermal interface material between and contacting the device die and the metal cap. The thermal interface material includes a first portion directly over an inner portion of the device die, and a second portion extending directly over a corner region of the device die. The first portion has a first thickness. The second portion has a second thickness greater than the first thickness.

Abstract: A package includes a package component, a device die over and bonded to the package component, a metal cap having a top portion over the device die, and a thermal interface material between and contacting the device die and the metal cap. The thermal interface material includes a first portion directly over an inner portion of the device die, and a second portion extending directly over a corner region of the device die. The first portion has a first thickness. The second portion has a second thickness greater than the first thickness.

Abstract: A semiconductor device includes a substrate, an electronic component, a ring structure and an adhesive layer. The substrate has a first surface. The electronic component is over the first surface of the substrate. The ring structure is over the first surface of the substrate, wherein the ring structure includes a first part having a first height, and a second part recessed from the bottom surface and having a second height lower than the first height. The adhesive layer is interposed between the first part of the ring structure and the substrate, and between the second part of the ring structure and the substrate.

Abstract: A three-dimensional chip stack includes a first chip bonded to a second chip to form an electrical interconnection therebetween. The bonded interconnection includes a first conductive pillar overlying a first substrate of the first chip, a second conductive pillar overlying a second substrate of the second chip, and a joint structure between the first conductive pillar and the second conductive pillar. The joint structure includes a first IMC region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region.

Abstract: A three-dimensional chip stack includes a first chip bonded to a second chip to form an electrical interconnection therebetween. The bonded interconnection includes a first conductive pillar overlying a first substrate of the first chip, a second conductive pillar overlying a second substrate of the second chip, and a joint structure between the first conductive pillar and the second conductive pillar. The joint structure includes a first IMC region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region.

Abstract: A three-dimensional chip stack includes a first chip bonded to a second chip to form an electrical interconnection therebetween. The bonded interconnection includes a first conductive pillar overlying a first substrate of the first chip, a second conductive pillar overlying a second substrate of the second chip, and a joint structure between the first conductive pillar and the second conductive pillar. The joint structure includes a first IMC region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region.

Abstract: A three-dimensional chip stack includes a first chip bonded to a second chip to form a bonded interconnection therebetween. The bonded interconnection includes a first conductive pillar overlying a first substrate of the first chip, a second conductive pillar overlying a second substrate of the second chip, and a joint structure between the first conductive pillar and the second conductive pillar. The joint structure includes a first IMC region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region.

Abstract: The signal line structure is disposed between a gate driver and a display area of a display. The signal line structure includes a substrate, first metal layers, a first insulation layer, second metal layers, a second insulation layer and third metal layers. The first metal layers are arranged in parallel and toward a first direction in the substrate. The first insulation layer is disposed in the substrate and covers the first metal layers. The second metal layers are disposed on the positions of the first insulation layer corresponding to the first metal layers. The second insulation layer is disposed on the second metal layers and the first insulation layer. The third metal layers are disposed on the positions corresponding to the second metal layers in the second insulation layer. The distance between two adjacent second metal layers is less than that between two adjacent first metal layers.

Abstract: An electrophoresis display apparatus includes an electronic-ink layer, a passive-matrix substrate, and a conducting layer. The passive-matrix substrate has an electrode surface, and the electrode surface has a plurality of electrodes. The conducting layer has a predetermined shape. The conducting layer is disposed between the electronic-ink layer and the electrode surface of the passive-matrix substrate and is used for transmitting the signals on the electrodes contacting the conducting layer to the electronic-ink layer, so that the electronic-ink layer can display an image with the predetermined shape.