Abstract: A non-volatile memory device may include a substrate, a first floating gate, a second floating gate, a third floating gate and a fourth floating gate. The substrate may include an active region. The first to fourth floating gates may be formed on the substrate. The first to fourth floating gates may be radially arranged to be partially overlapped with the active region. The first floating gate and the third floating gate may face each other in a first direction. The first floating gate and the third floating gate may have asymmetrically planar shapes. The first floating gate and the second floating gate may face each other in a second direction substantially perpendicular to the first direction. The first floating gate and the second floating gate may have asymmetrically planar shapes. The third floating gate and the fourth floating gate may face each other in the second direction. The third floating gate and the fourth floating gate may have asymmetrically planar shapes.

Abstract: An image sensor is provided to include an active region which comprises: a floating diffusion region; a transfer transistor gate region; transistor active regions; and a well-tap region. The transfer transistor gate region may have a diagonal bar shape to isolate the floating diffusion region in a first corner of the active region. The well-tap region may be positioned between the transfer transistor gate region and the transistor active regions, and isolate the transfer transistor gate region from the transistor active regions.

Abstract: Memory devices are disclosed. In an embodiment of the disclosed technology, a memory device may include a substrate including an active region, and a first floating gate, a second floating gate, a third floating gate and a fourth floating gate formed on the substrate, arranged to partially overlap with the active region. The first floating gate and the third floating gate are arranged in a first direction at one side of the active region and asymmetrical about a center of the active region, and the second floating gate and the fourth floating gate are arranged in the first direction at another side of the active region and asymmetrical about the center of the active region.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a memory cell string including a plurality of memory cells coupled to a plurality of word lines, a peripheral circuit configured to perform an operation that applies an operating voltage to a selected word line and applying a pass voltage to unselected word lines, among the plurality of word lines, and an operation controller configured to control the peripheral circuit to perform, after the operation has been performed, a discharge operation that sequentially decreases voltages of the plurality of word lines that range from at least one central word line located in a central portion in relation to the memory cell string to a word line, among the plurality of word lines, located in an outermost portion in relation to the memory cell string, adjacent to a select line.

Abstract: An image sensing device includes a pixel array including a plurality of unit pixels consecutively arranged and structured to generate an electrical signal in response to incident light by performing photoelectric conversion of the incident light. The unit pixels are isolated from each other by first device isolation structures. Each of the unit pixels includes a photoelectric conversion element structured to generate photocharges by performing photoelectric conversion of the incident light, a floating diffusion region structured to receive the photocharges, a transfer transistor structured to transfer the photocharges generated by the photoelectric conversion element to the floating diffusion region, and a well tap region structured to apply a bias voltage to a well region. The well tap region is disposed at a center portion of a corresponding unit pixel.

Abstract: An image sensing device includes a pixel array including a plurality of unit pixels consecutively arranged and structured to generate an electrical signal in response to incident light by performing photoelectric conversion of the incident light. The unit pixels are isolated from each other by first device isolation structures. Each of the unit pixels includes a photoelectric conversion element structured to generate photocharges by performing photoelectric conversion of the incident light, a floating diffusion region structured to receive the photocharges, a transfer transistor structured to transfer the photocharges generated by the photoelectric conversion element to the floating diffusion region, and a well tap region structured to apply a bias voltage to a well region. The well tap region is disposed at a center portion of a corresponding unit pixel.

Abstract: A semiconductor memory device may include a second conductive type first well, a second conductive type third well, a first conductive type second well, a floating gate and a selection gate. The first well may include a first active region. The third well may include a third active region. The second well may be arranged between the first well and the third well. The second well may include a second active region. The floating gate may be overlapped with the first active region, the second active region and the third active region. The selection gate may be overlapped with the second active region. The selection gate and the floating gate may be arranged side by side. A second overlap area between the second active region and the floating gate may be larger than a third overlap area between the third active region and the floating gate.

Abstract: An image sensor includes a first transfer gate formed over a substrate, and including a first projection; a second transfer gate formed over the substrate, neighboring the first transfer gate, and including a second projection; and a floating diffusion formed in the substrate, and partially overlapping with the first transfer gate and the second transfer gate, wherein the first projection and the second projection face each other.

Abstract: An image sensing device includes a floating diffusion node, a reset circuit coupled between a supply terminal of a high voltage and the floating diffusion node, and suitable for resetting the floating diffusion node with the high voltage during a reference period based on a reset control signal, a photodiode coupled between a supply terminal of a low voltage and a coupling node, and suitable for generating a photocharge based on incident light during an exposure period, a transmission block coupled between the coupling node and the floating diffusion node, and suitable for transmitting the photocharge to the floating diffusion node during a transmission period based on a transmission control signal, and a selection circuit coupled between an input terminal of a boost control signal and an output terminal of a pixel signal, and suitable for generating the pixel signal with a boost voltage greater than the high voltage during the transmission period based on a selection control signal and a voltage applied to t

Abstract: An image sensor includes a first transfer gate formed over a substrate, and including a first projection; a second transfer gate formed over the substrate, neighboring the first transfer gate, and including a second projection; and a floating diffusion formed in the substrate, and partially overlapping with the first transfer gate and the second transfer gate, wherein the first projection and the second projection face each other.

Abstract: Memory devices are disclosed. In an embodiment of the disclosed technology, a memory device may include a substrate including an active region, and a first floating gate, a second floating gate, a third floating gate and a fourth floating gate formed on the substrate, arranged to partially overlap with the active region. The first floating gate and the third floating gate are arranged in a first direction at one side of the active region and asymmetrical about a center of the active region, and the second floating gate and the fourth floating gate are arranged in the first direction at another side of the active region and asymmetrical about the center of the active region.

Abstract: An image sensing device is provided to include a pixel region including image pixels and a peripheral region located outside of the pixel region. The peripheral region includes logic circuits located to receive the pixel signals from the pixel region and configured to process the pixel signals, and a capacitor located adjacent to the logic circuits. The capacitor includes an active region including a first impurity region and a second impurity region formed over the first impurity region, a recessed structure including a portion formed in the active region, the portion including a conductive layer extending along a direction that the first impurity region and the second impurity region are stacked and an insulation layer formed between the conductive layer and the active region, and a first junction formed in the active region and spaced apart from the recessed structure by a predetermined distance.

Abstract: An image sensing device includes a pixel array including a plurality of unit pixels consecutively arranged and structured to generate an electrical signal in response to incident light by performing photoelectric conversion of the incident light. The unit pixels are isolated from each other by first device isolation structures. Each of the unit pixels includes a photoelectric conversion element structured to generate photocharges by performing photoelectric conversion of the incident light, a floating diffusion region structured to receive the photocharges, a transfer transistor structured to transfer the photocharges generated by the photoelectric conversion element to the floating diffusion region, and a well tap region structured to apply a bias voltage to a well region. The well tap region is disposed at a center portion of a corresponding unit pixel.

Abstract: An image sensing device is provided to include a pixel region and a peripheral region located outside of the pixel region. The peripheral region includes logic circuits located to receive a pixel signals from the pixel region and configured to process the pixel signals and a capacitor located adjacent to the logic circuits. The capacitor includes an active region, a recessed structure, and a first junction. The active region includes a first impurity region and a second impurity region formed over the first impurity region. The recessed structure is at least partly disposed in the active region and including a first portion disposed in the active region and including a conductive material and a second portion surrounding the first portion and including an insulation material. The first junction is formed in the active region and spaced apart from the recessed structure by a predetermined distance.

Abstract: An image sensor includes a first transfer gate formed over a substrate, and including a first projection; a second transfer gate formed over the substrate, neighboring the first transfer gate, and including a second projection; and a floating diffusion formed in the substrate, and partially overlapping with the first transfer gate and the second transfer gate, wherein the first projection and the second projection face each other.

Abstract: An image sensor includes a first transfer gate formed over a substrate, and including a first projection; a second transfer gate formed over the substrate, neighboring the first transfer gate, and including a second projection; and a floating diffusion formed in the substrate, and partially overlapping with the first transfer gate and the second transfer gate, wherein the first projection and the second projection face each other.

Abstract: A nonvolatile memory device includes an active region extending in a first direction and including a source region and a drain region that are respectively disposed at both ends of the active region, a gate electrode pattern extending in a second direction and disposed between the source region and the drain region, wherein the second direction extends across the first direction, a gate insulation pattern disposed between the gate electrode pattern and the active region, a source contact plug and a drain contact plug respectively coupled to the source region and the drain region, and a coupling contact plug disposed over the gate electrode pattern and insulated from the gate electrode pattern.

Abstract: An image sensing device is provided to include a pixel region and a peripheral region located outside of the pixel region. The peripheral region includes logic circuits located to receive a pixel signals from the pixel region and configured to process the pixel signals and a capacitor located adjacent to the logic circuits. The capacitor includes an active region, a recessed structure, and a first junction. The active region includes a first impurity region and a second impurity region formed over the first impurity region. The recessed structure is at least partly disposed in the active region and including a first portion disposed in the active region and including a conductive material and a second portion surrounding the first portion and including an insulation material. The first junction is formed in the active region and spaced apart from the recessed structure by a predetermined distance.

Abstract: An image sensing device is provided to include a pixel region including image pixels and a peripheral region located outside of the pixel region. The peripheral region includes logic circuits located to receive the pixel signals from the pixel region and configured to process the pixel signals, and a capacitor located adjacent to the logic circuits. The capacitor includes an active region including a first impurity region and a second impurity region formed over the first impurity region, a recessed structure including a portion formed in the active region, the portion including a conductive layer extending along a direction that the first impurity region and the second impurity region are stacked and an insulation layer formed between the conductive layer and the active region, and a first junction formed in the active region and spaced apart from the recessed structure by a predetermined distance.

Abstract: An image sensor is provided to include an active region which comprises: a floating diffusion region; a transfer transistor gate region; transistor active regions; and a well-tap region. The transfer transistor gate region may have a diagonal bar shape to isolate the floating diffusion region in a first corner of the active region. The well-tap region may be positioned between the transfer transistor gate region and the transistor active regions, and isolate the transfer transistor gate region from the transistor active regions.