Abstract: A method for forming a contact hole of a semiconductor device, includes forming a hard mask over an etch target layer, forming a first line pattern over the hard mask, forming a second line pattern over the hard mask and the first line pattern in a direction crossing the first line pattern, forming a mesh-type hard mask pattern by etching the hard mask using the first and second line patterns as etch barriers, and forming a contact hole by etching the etch target layer using the mesh-type hard mask pattern as an etch barrier.

Abstract: A method for forming contact holes in a semiconductor device includes forming a hard mask layer over an etch target layer, forming a first line pattern in the hard mask layer by etching a portion of the hard mask layer through a primary etch process, forming a second line pattern crossing the first line pattern by etching the hard mask layer including the first line pattern through a secondary etch process, and etching the etch target layer by using the hard mask layer including the first line pattern and the second line pattern as an etch barrier.

Abstract: An output driver circuit includes a predriver control signal generation unit receiving a pull-up code signal, a pull-down code signal, a predriver selection signal and a read control signal and generating a pull-up control signal and a pull-down control signal; a predriver driven in response to the pull-up control signal and the pull-down control signal and receiving an internal data to drive a pull-up driving signal and a pull-down driving signal; and a driver receiving the pull-up driving signal and the pull-down driving signal and driving an output data outputted to a DQ pad, wherein the pull-up control signal and the pull-down control signal are enabled when the predriver is selected in a read operation period and a preset combination of the code signals is inputted.

Abstract: A method for forming a capacitor in a semiconductor device comprises forming an inter-layer layer on a semi-finished substrate; etching the inter-layer insulation layer to form a plurality of first contact holes; forming a first insulation layer on sidewalls of the first contact holes; forming a plurality of storage-node contact plugs filled into the first contact holes; forming a second insulation layer with a different etch rate from the first insulation layer over the storage-node contact plugs; forming a third insulation layer on the second insulation layer; sequentially etching the third insulation layer and the second insulation layer to form a plurality of second contact holes exposing the storage-node contact plugs; and forming the storage node on each of the second contact holes.

Abstract: An output driver circuit includes a predriver control signal generation unit receiving a pull-up code signal, a pull-down code signal, a predriver selection signal and a read control signal and generating a pull-up control signal and a pull-down control signal; a predriver driven in response to the pull-up control signal and the pull-down control signal and receiving an internal data to drive a pull-up driving signal and a pull-down driving signal; and a driver receiving the pull-up driving signal and the pull-down driving signal and driving an output data outputted to a DQ pad, wherein the pull-up control signal and the pull-down control signal are enabled when the predriver is selected in a read operation period and a preset combination of the code signals is inputted.

Abstract: A method for fabricating a three dimensional type capacitor is provided. The method includes forming a first insulation layer including first contact layers over a substrate, forming a second insulation layer over the first insulation layer, forming second contact layers by using a material having an etch selectivity different from the first contact layers such that the second contact layers are connected with the first contact layers within the second insulation layer, forming an etch stop layer over the second insulation layer and the second contact layers, forming a third insulation layer over the etch stop layer, etching the third insulation layer and the etch stop layer to form first contact holes exposing the second contact layers, etching the exposed second contact layers to form second contact holes exposing the first contact holes, and forming bottom electrodes over the inner surface of the second contact holes.

Abstract: A method for fabricating a semiconductor device includes forming a first pattern over a substrate, forming an oxide-based layer over the first pattern, forming a hard mask layer over the oxide-based layer, etching the hard mask layer at a first substrate temperature, and etching the oxide-based layer to form a second pattern, wherein the oxide-based layer is etched at a second substrate temperature which is greater than the first substrate temperature using a gas including fluorine (F) and carbon (C) as a main etch gas.

Abstract: A first insulation layer is formed on a substrate structure including an inter-layer insulation layer and a storage node contact plug. The first insulation layer is etched to form a first opening exposing a portion of the storage node contact plug. The first opening is filled with an organic polymer layer. An etch stop layer and a second insulation layer are formed on the organic polymer layer and the first insulation layer. A photoresist pattern is formed on the second insulation layer. The second insulation layer and the etch stop layer are etched to form a second opening exposing a portion of the organic polymer layer. The photoresist pattern and the organic polymer layer are removed, thereby extending a portion of the second opening. A storage node is formed over the extended second opening and the second insulation layer.

Abstract: A semiconductor memory device capable of preventing bridge formations in a peripheral circuit region includes: a cell region; a peripheral circuit region adjacent to the cell region; and a plurality of line patterns formed in the cell region and the peripheral circuit region, wherein a spacing distance between the line patterns is at least onefold greater than a width of the line pattern.

Abstract: A method for fabricating a fine pattern in a semiconductor device includes forming a first polymer layer and a second polymer layer over an etch target layer. The second polymer layer is patterned at a first substrate temperature. The first polymer layer is etched at a second substrate temperature using an etch gas that does not include oxygen (O2). The first polymer layer is etched using the patterned second polymer layer as an etch mask. The etch target layer is then etched using the etched first polymer layer and the etched second polymer layer as an etch mask.

Abstract: A method for forming a contact hole of a semiconductor is provided. Conductive patterns are formed over a substrate. An insulation layer is formed over the substrate to bury the conductive patterns. A hard mask including an amorphous carbon layer and an oxide based layer are formed in sequential order over the insulation layer and the conductive pattern. The amorphous carbon layer and the oxide layer are selectively etched to form a mask pattern. The insulation layer is etched using the mask pattern as a mask to form a contact hole.

Abstract: Disclosed herein are an N-terminal modified PEG-TRAIL conjugate and a preparation method and use thereof. The PEG-TAIL conjugate has pharmaceutical activity identical or similar to that of native TRAIL (TNF-related apoptosis-inducing ligand) with extended in vivo half-life and enhanced stability. Compared to native TRAIL, the PEG-TAIL conjugate exhibits high solubility and solution stability, with highly improved pharmacokinetic profiles. Thus, the PEG-TAIL conjugate may be very useful for preventing and treating proliferative diseases and autoimmune diseases.

Abstract: A method for forming a contact hole of a semiconductor device includes: forming a lower pattern over a substrate; forming a spin-on-glass (SOG) layer over the lower pattern; performing a first curing process on the SOG layer; forming an opening exposing a portion of the SOG layer; performing a second curing process on the SOG layer corresponding to a lower portion of the opening; and forming a contact hole exposing the lower pattern.

Abstract: A method for fabricating a semiconductor device is provided. The method includes: preparing a substrate defined as active regions and inactive regions and provided with a plurality of conductive patterns; forming a buffer layer over the plurality of conductive patterns; forming an organic material having fluidity better than that of a photoresist layer on the buffer layer; flowing the organic material between the conductive patterns through a thermal treatment process, thereby filling a portion of each gap between the conductive patterns; forming the photoresist layer over the organic material and the buffer layer; forming a plurality of photoresist patterns opening the active regions through a photo-exposure process and a developing process; and performing an ion-implantation process using the plurality of photoresist patterns, thereby forming a plurality of junction regions in the active regions of the substrate.

Abstract: A method for fabricating a three dimensional type capacitor is provided. The method includes forming a first insulation layer including first contact layers over a substrate, forming a second insulation layer over the first insulation layer, forming second contact layers by using a material having an etch selectivity different from the first contact layers such that the second contact layers are connected with the first contact layers within the second insulation layer, forming an etch stop layer over the second insulation layer and the second contact layers, forming a third insulation layer over the etch stop layer, etching the third insulation layer and the etch stop layer to form first contact holes exposing the second contact layers, etching the exposed second contact layers to form second contact holes exposing the first contact holes, and forming bottom electrodes over the inner surface of the second contact holes.

Abstract: A method is used in forming a fine pattern in a semiconductor device. The method includes forming an etch target layer; forming a photoresist pattern over the etch target layer; forming a polymer pattern including silicon-oxygen (Si—O) bonds on sidewalls of the photoresist pattern; removing the photoresist pattern; and etching the etch target layer using the polymer pattern as an etch mask.

Abstract: A semiconductor device capable of preventing a bridge generation during performing an etching process to form a plurality of gate structures on a substrate divided into an active region and a field region and an electrical short between a contact plug and the individual gate structure in the field region and a method for fabricating the same are provided. The semiconductor device includes: a substrate provided with an active region and a field region; a field oxide layer formed in the field region in such a way that the field oxide layer is recessed to be lower than a surface of the substrate disposed in the active region; and a plurality of gate structures formed on the field oxide layer and the substrate in the active region.

Abstract: A method for forming a fine pattern in a semiconductor device includes forming a first polymer layer over an etch target layer, the first polymer layer including a carbon-rich polymer layer, forming a second polymer layer over the first polymer layer, the second polymer layer including a silicon-rich polymer layer, patterning the second polymer layer, oxidizing surfaces of the patterned second polymer layer, etching the first polymer layer using the patterned second polymer layer comprising the oxidized surfaces, and etching the etch target layer using the patterned second polymer layer comprising the oxidized surfaces and the etched first polymer layer.

Abstract: A method for fabricating a three dimensional type capacitor is provided. The method includes forming a first insulation layer including first contact layers over a substrate, forming a second insulation layer over the first insulation layer, forming second contact layers by using a material having an etch selectivity different from the first contact layers such that the second contact layers are connected with the first contact layers within the second insulation layer, forming an etch stop layer over the second insulation layer and the second contact layers, forming a third insulation layer over the etch stop layer, etching the third insulation layer and the etch stop layer to form first contact holes exposing the second contact layers, etching the exposed second contact layers to form second contact holes exposing the first contact holes, and forming bottom electrodes over the inner surface of the second contact holes.

Abstract: A method for fabricating a conducting layer pattern using a hard mask of which a upper surface is flattened by the use of ArF exposure light source.