Abstract: Disclosed is a method for fabricating a semiconductor device capable of preventing an inter-layer insulation layer from being damaged during a wet cleaning process due to a density difference created by reliance on a thickness of a SOG layer subjected to a curing process and of overcoming defects caused by an improper contact opening in a certain region and a punch taken place by micro voids of an APL layer. Particularly, the method includes the steps of: forming a plurality of conductive structure on a substrate; forming a spin-on-glass layer; curing the spin-on-glass layer; forming an advanced-planarization-layer on the spin-on-glass layer; and forming a plurality of contact holes by selectively etching the advanced-planarization-layer and the spin-on-glass layer, thereby exposing portions of the substrate.

Abstract: Disclosed is a method for fabricating a semiconductor device having at least one contact holes formed by employing a self-aligned contact (SAC) etching process. The contact holes are formed through the shortened number of sequential steps by using different process recipes. First, an anti-reflective coating (ARC) layer formed on a substrate structure prepared sequentially with a substrate, conductive structures, an etch stop layer and an inter-layer insulation layer is etched by employing an etch gas of CF4, O2, CO and Ar. Then, a portion of an inter-layer insulation layer is etched with use of an etch gas of CF4 and O2. The rest portion of the inter-layer insulation layer is subsequently etched by using a different etch gas of C4F6, CH2F2, O2 and Ar to thereby form at least one contact hole exposing the etch stop layer.

Abstract: The present invention relates to a method for fabricating a semiconductor device with a fine pattern. The method includes the steps of: (a) forming a semiconductor substrate structure including a substrate, a nitride layer for forming a hard mask, a plurality of conductive patterns, an etch stop layer, an inter-layer insulation layer, an anti-reflective coating (ARC) layer and a photoresist pattern; (b) selectively etching the ARC layer and the nitride layer with use of the photoresist pattern as an etch mask to form a hard mask; (c) removing the photoresist pattern and the ARC layer; (d) etching the inter-layer insulation layer disposed between the conductive patterns by using the hard mask as an etch mask to form a contact hole exposing the etch stop layer; (e) removing the etch stop layer formed at a bottom area of the contact hole to expose the substrate; and (f) forming a plug electrically contacted to the exposed substrate, wherein the steps (b) and (d) to (e) proceeds in an in situ condition.

Abstract: A method for fabricating a semiconductor device capable of preventing a hard mask from being lifted and patterns from being defective. Particularly, an inter-layer insulation layer and an etch stop layer formed on a substrate structure provided with conductive structures are first planarized. Then, a hard mask made of a nitride-based material is formed by using a photoresist pattern and an anti-reflective coating layer as an etch mask. After the hard mask formation, the photoresist pattern and the anti-reflective coating layer are removed. Subsequently, a SAC etching process is performed to etch the inter-layer insulation layer with use of the hard mask as an etch mask, thereby obtaining a contact hole exposing the etch stop layer disposed between the conductive structures. The exposed etch stop layer is removed through the use of a blanket etch-back process, and a cleaning process is applied thereafter.

Abstract: The present invention provides a method for fabricating a semiconductor device capable of minimizing losses of a gate electrode and a hard mask during a self align contact (SAC) formation process. For this effect, the present invention includes the steps of: forming a plurality of conductive patterns on a substrate; forming hard masks on the conductive patterns; forming an organic based dielectric layer on the substrate including the conductive patterns and the hard mask; forming an oxide based insulation layer on the organic based dielectric layer; selectively etching the insulation layer so as to expose the organic based dielectric layer allocated between the conductive patterns; and selectively etching the exposed organic based dielectric layer to form a contact hole that exposes the surfaces of the substrate between the conductive patterns with an O2 gas as a main etching gas.

Abstract: A method for fabricating a semiconductor device capable of preventing an inter-layer insulation layer from being damaged during a wet cleaning process. The method includes the steps of: forming a plurality of conductive structures on a substrate; forming an etch stop layer and a flowable insulation layer on the plurality of conductive structures subsequently; forming a photoresist pattern on the flowable insulation layer; forming a plurality of contact holes by etching the flowable insulation layer with use of the photoresist pattern as an etch mask, thereby exposing portions of the etch stop layer; forming at least one barrier layer on the contact holes; removing said at least one barrier layer and the etch stop layer disposed at each bottom portion of the contact holes to thereby expose the substrate; and cleaning the contact holes.

Abstract: Disclosed is a method for fabricating a semiconductor device with an improved tolerance to a wet cleaning process. For a contact formation such as a gate structure, a bit line or a metal wire, a spin on glass (SOG) layer employed as an inter-layer insulation layer becomes tolerant to the wet cleaning process by allowing even a bottom part of the SOG layer to be densified during a curing process. The SOG layer is subjected to the curing process after a maximum densification thickness of the SOG layer is obtained through a partial removal of the initially formed SOG layer or through a multiple SOG layer each with the maximum densification thickness. After the SOG layer is cured, a self-aligned contact etching process is performed by using a photoresist pattern singly or together with a hard mask.

Abstract: The present invention provides a method for fabricating a semiconductor device with use of an ArF light source capable of minimizing deformations of a photoresist pattern for ArF during an etching process. Also, when forming the pattern, C5F8 gas is used at a main etching step to compensate etch tolerance of the photoresist for ArF. By controlling process recipe properly, it is possible to minimize pattern deformations as simultaneously as to form a micronized pattern. To compensate the etch tolerance of the photoresist for ArF weaker than that of a photoresist for KrF, the main etching step is divided into three sub-steps, thereby providing a method for minimizing the pattern deformations when duplicating the pattern.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of first plugs contacted to a substrate by passing through a first inter-layer insulation layer; forming a second inter-layer insulation layer on the first plugs; forming a conductive pattern contacted to a group of the first plugs by etching selectively the second inter-layer insulation layer; and forming a contact hole exposing a surface of the first plug that is not contacted to the conductive pattern by etching selectively the second insulation layer with use of a dry-type and wet-type etch process, wherein an attack barrier layer is formed on between the first inter-layer insulation layer and the second inter-layer insulation layer to thereby prevent an incidence of attack to the first interlayer insulation layer contacted to the first plug during the wet-type etch process for forming the contact hole.

Abstract: The present invention provides a semiconductor memory device capable of preventing bridge formations in a peripheral circuit region and improving a process margin and a method for fabricating the same. The semiconductor memory device includes: a cell region; a peripheral circuit region adjacent to the cell region; and a plurality of line patterns formed in the cell region and the peripheral circuit region, wherein a spacing distance between the line patterns is at least onefold greater than a width of the line pattern.

Abstract: A method for fabricating a semiconductor device by simultaneously forming via holes in a multi-layered structure having depth differences without requiring additional process steps. Steps to achieve this effect include forming a first conductive layer; forming a first etching protection layer on the first conductive layer; forming a first insulating layer; forming a second conductive layer on the first insulating layer; forming a second etching protection layer on the second conductive layer, wherein etching protection efficiency of the second protection layer is higher than that of the first etching protection layer; forming a second insulating layer; and forming a first and a second via hole respectively exposing the first and the second conductive layer by selectively etching the first and second insulating layer.

Abstract: A method for fabricating a semiconductor device capable of preventing an electric short circuit between a storage node contact plug and a conductive pattern by forming an attack barrier layer or use of an insulation layer having a flow-fill property. The attack barrier layer for preventing the electric short circuit is formed by employing two methods. First, the attack barrier layer is formed on an entire surface of a structure containing the plugs after the CMP process and the cleaning process. Second, the attack barrier layer is formed on a structure including a storage node contact hole such that the attack barrier layer fills the lost portion of the insulating material-based layer. Also, instead of using the attack barrier layer, the insulation layer having a flow-fill property is deposited after the cleaning process.

Abstract: The present invention relates to a method for fabricating a semiconductor device with realizable advanced fine patterns.

Abstract: The present invention is related to a method for fabricating a semiconductor device capable of preventing a bit line pattern from being attacked during a storage node contact hole formation. The method includes the steps of: forming a bit line insulation layer on a substrate structure having a plurality of plugs; forming a group of trenches exposing a group of the plugs by etching the bit line insulation layer; burying each trench by a conductive material to form a bit line electrically connected to the exposed plug; isolating the bit line by performing a chemical mechanical polishing process until the bit line insulation layer is exposed; forming an inter-layer insulation layer on the above structure including the bit line; and etching selectively the inter-layer insulation layer and the bit line insulation layer to form storage node contact holes exposing another group of the plugs.

Abstract: The present invention provides a method for fabricating a semiconductor device capable of preventing a pattern at an edge area of a wafer from being lifted and acting as a particle source. The present invention includes the steps of: preparing a wafer having a first area and a second area, wherein the first area has lower topology than the second area; forming a target layer on the wafer; and patterning the target layer through a photolithography process so to form a number of first patterns in a line shape at the second area and to form a number of second patterns in a closed loop shape at the first area.

Abstract: The present invention is related to a method for fabricating a semiconductor device capable of preventing occurrences of void and seam phenomena caused by a negative slope of an insulation layer or a bowing profile phenomenon in a cross-sectioned etch profile of a contact hole. To achieve this effect, the attack barrier layer or the capping layer is additionally deposited on the profile containing self-aligned contact holes in order to prevent an undercut of the inter-layer insulation layer, which is a main cause of the seam generations. Also, the attack barrier layer has a function of preventing the inter-layer insulation layer from being attacked during the wet cleaning/etching process. Ultimately, it is possible to improve device characteristics with the prevention of the seam generations.

Abstract: The present invention provides a method for fabricating a semiconductor device capable of improving a gap-fill property of a conductive wire. To achieve this effect, the inventive method includes the steps of: forming a plurality of conductive patterns on a substrate in the first region and the second region, wherein each of the conductive patterns includes sequentially stacked layers of a conductive layer and a hard mask; removing the hard mask in the second region to expose the conductive layer; forming a diffusion barrier layer on the exposed conductive layer; depositing an insulation layer on the entire resulting substrate structure in the first region and the second region; selectively etching the insulation layer in the second region to form an opening exposing the diffusion barrier layer; and forming a conductive wire electrically connected to the diffusion barrier layer through the opening.

Abstract: The present invention provides a method for reducing loading capacitance.

Abstract: The present invention provides a semiconductor device capable of preventing a pattern collapse phenomenon in a cell edge area in which a pattern is more fragile. The inventive semiconductor device having a lower pattern density in an edge area than in a central area of a wafer includes a plurality of bar-type patterns allocated at a predetermined distance in the central area of the wafer; a plurality of dummy patterns formed in the edge area; and a plurality of a connection pattern for coupling at least two of the bar-type patterns to each other, wherein the connection patterns of the plurality of dummy patterns is allocated in a zigzag fashion.

Abstract: The present invention provides a method for fabricating a semiconductor device capable of securing a bottom contact area of a storage node contact as well as of preventing losses of a bit line hard mask insulation layer. These effects are achieved by planarizing an inter-layer insulation layer, which is filled into etched portions formed between conductive patterns, with the bit line hard mask insulation layer through a CMP process. This planarization process decreases a thickness of an etch target to thereby provide more vertical etch profile compared to a typical etch profile that is tapered or inclined at a bottom contact area. As a result of the decreased thickness of the etch target and the more vertical etch profile, it is possible to obtain the wider bottom contact area and prevent losses of the bit line hard mask insulation layer.