Abstract: A method for fabricating a semiconductor device capable of minimizing deformations of a photoresist pattern and losses of a hard mask. The method includes the steps of: forming an insulating layer for a hard mask on an etch-target layer; forming a sacrificial layer on the insulating layer; forming a photoresist pattern on the sacrificial layer; forming at least one sacrificial hard mask by etching the sacrificial layer with the photoresist pattern as an etching mask; forming the hard mask by etching the insulating layer with the sacrificial hard mask as an etching mask; and forming a predetermined number of patterns by etching the etch-target layer with use of the sacrificial hard mask and the hard mask as etching masks.

Abstract: The present invention provides a semiconductor memory device capable of preventing bridge formations in a peripheral circuit region and improving a process margin and a method for fabricating the same. The semiconductor memory device includes: a cell region; a peripheral circuit region adjacent to the cell region; and a plurality of line patterns formed in the cell region and the peripheral circuit region, wherein a spacing distance between the line patterns is at least onefold greater than a width of the line pattern.

Abstract: A dual damascene process is disclosed which reduces capacitance increases caused by excess and unnecessary remnants of an etching stop layer and which also improves multi-level interconnect structures by removing the etching stop layer except for a portion that surrounds the via hole. This reduces or eliminates capacitance increase and avoids erosion of underlying interlayer insulating layers during formation of an upper, wider trench.

Abstract: A method for fabricating a semiconductor device capable of preventing an inter-layer insulation layer from being damaged during a wet cleaning process. The method includes the steps of: forming a plurality of conductive structures on a substrate; forming an etch stop layer and a flowable insulation layer on the plurality of conductive structures subsequently; forming a photoresist pattern on the flowable insulation layer; forming a plurality of contact holes by etching the flowable insulation layer with use of the photoresist pattern as an etch mask, thereby exposing portions of the etch stop layer; forming at least one barrier layer on the contact holes; removing said at least one barrier layer and the etch stop layer disposed at each bottom portion of the contact holes to thereby expose the substrate; and cleaning the contact holes.

Abstract: Disclosed are a semiconductor device with a three-dimensional storage node and a method for fabricating the same. The semiconductor device includes: an inter-layer insulation layer formed on a substrate; a first plug contacted to the substrate by penetrating into the inter-layer insulation layer; an insulation layer formed on the first plug; a second plug contacted to the first plug by penetrating into the insulation layer and projected in an upward direction from a surface level of the insulation layer; a barrier layer formed on the second plug and the insulation layer; and a storage node formed on the second plug to be connected with the second plug through a portion where the barrier layer is removed.

Abstract: Disclosed is a method for forming a plurality of contact holes in a semiconductor device. The method includes the steps of: forming an oxide-based layer on a substrate; forming an organic polymer layer on the oxide-based layer; forming a photoresist pattern on the organic polymer layer to form the plurality of contact holes; etching the organic polymer layer by using the photoresist pattern as an etch mask, thereby forming a hard mask; etching the oxide-based layer by using the photoresist pattern and the hard mask as an etch mask; and removing the photoresist pattern and the hard mask by performing a photoresist strip process, thereby obtaining the plurality of contact holes.

Abstract: Disclosed are a semiconductor device and a method for fabricating the same capable of preventing a bridge generation between plugs during forming a plurality of hole type contact plugs for forming storage nodes. The semiconductor device includes: a first gate structure and a second gate structure placed in parallel by a predetermined space; a plurality of bit lines placed on upper portions of the first gate structure and the second gate structure with crossing the first gate structure and the second gate structure; a first cell contact plug and a second cell contact plug located through the plurality of bit lines and formed between the first gate structure and the second gate structure; and an inter-layer insulation layer provided with a first storage node contact hole and a second storage node contact hole connected with each other by etching the inter-layer insulation layer on upper portions of the plurality of bit lines.

Abstract: The present invention provides a semiconductor memory device capable of preventing bridge formations in a peripheral circuit region and improving a process margin and a method for fabricating the same. The semiconductor memory device includes: a cell region; a peripheral circuit region adjacent to the cell region; and a plurality of line patterns formed in the cell region and the peripheral circuit region, wherein a spacing distance between the line patterns is at least onefold greater than a width of the line pattern.

Abstract: The present invention is a method for testing a contact open capable of effectively testing a contact open defect in an In-line as securing a mass productivity. The method includes the steps of: performing a photolithography process for forming a contact; forming a contact hole by performing a contact etching process after sampling at least one wafer; depositing a conductive layer on the wafer provided with the contact hole; isolating the conductive layer within the contact hole; performing a test for testing a contact open interface to check whether a remaining layer is existed in an interface between the conductive layer and a lower structure of the conductive layer; and performing a process for etching the contact of a main lot based on a test result.

Abstract: Disclosed is a method for fabricating a semiconductor device with an improved tolerance to a wet cleaning process. For a contact formation such as a gate structure, a bit line or a metal wire, a spin on glass (SOG) layer employed as an inter-layer insulation layer becomes tolerant to the wet cleaning process by allowing even a bottom part of the SOG layer to be densified during a curing process. The SOG layer is subjected to the curing process after a maximum densification thickness of the SOG layer is obtained through a partial removal of the initially formed SOG layer or through a multiple SOG layer each with the maximum densification thickness. After the SOG layer is cured, a self-aligned contact etching process is performed by using a photoresist pattern singly or together with a hard mask.

Abstract: A device, arrangement and method may control bus request timing to disperse bus access timing, so that adverse effects of concentration-on-bus phenomenon may be avoided. The device may include a bus request signal generating circuit may generate a bus request signal under control of a counter, and a pulse signal generating circuit may generate a pulse signal as a function of a number of times the bus request signal generating circuit has generated a bus request signal and a first threshold value. The device may include a determining circuit and a control circuit. The determining circuit may generate a determination result representing whether a given process period for generating the bus request signal has ended as a function of the pulse signal. The control circuit may control the counter to adjust the process period for generating the bus request signal, based on the determination result.

Abstract: A method for forming a photoresist pattern with minimally reduced transformations through the use of ArF photolithography, including the steps of: forming an organic anti-reflective coating layer on a an etch-target layer already formed on a substrate; coating a photoresist for ArF on the organic anti-reflective coating layer; exposing the photoresist with ArF laser; forming a first photoresist pattern by developing the photoresist, wherein portions of the organic anti-reflective coating layer are revealed; etching the organic anti-reflective coating layer with the first photoresist pattern as an etch mask and forming a second photoresist pattern by attaching polymer to the first photoresist pattern, wherein the polymer is generated during etching the organic anti-reflection coating layer with an etchant including O2 plasma; and etching the etch-target layer by using the second photoresist pattern as an etch mask.

Abstract: The method forming a contact pad of a semiconductor device, including forming a plurality of conductive layer patterns displaced on a silicon substrate with adjoining to each other; forming an insulating layer on a top of the conductive layer patterns; depositing a material layer serving as a hard mask on the insulating layer; forming a photoresist pattern between the conductive layer patterns on the hard mask material layer to form a contact hole; defining an area for forming a contact by forming by etching the hard mask material layer with utilizing the photoresist pattern as an etching mask; removing the photoresist pattern; exposing the silicon substrate by etching the insulating layer with utilizing the hard mask as an etching mask to thereby form an open portion; forming a polymer layer on the open portion; exposing the silicon substrate by removing the hard mask and the polymer layer by implementing an etch back process; and forming a contacted pad on the exposed silicon substrate.

Abstract: Disclosed is a method for fabricating a semiconductor device with an improved process margin obtained by preventing damage to an inter-layer insulation layer during a wet cleaning process. Particularly, the method includes the steps of: forming a plurality of a first conductive pattern having a stack pattern of a first conductive and a first hard mask; forming a first inter-layer insulation layer of a good gap-fill property with a height between the first conductive material and the first hard mask on the first conductive layer; forming a second inter-layer insulation layer; forming a second conductive layer contacted the first conductive layer between the plurality of the first conductive patterns as passing through the first and the second inter-layer insulation layers; forming a third inter-layer insulation layer; forming a plurality of second conductive patterns; forming a fourth inter-layer insulation layer; and forming a third conductive layer contacted to the second conductive layer.

Abstract: Disclosed is a method for fabricating a semiconductor device without damaging a hard mask of a conductive structure. The method includes the steps of: forming a plurality of conductive structures on a substrate, each conductive structure including a conductive layer and a hard mask; sequentially forming a first nitride layer, an oxide layer, a second nitride layer, and an etch stop layer on the plurality of conductive structures; forming an inter-layer insulation layer on the etch stop layer; removing a portion of the inter-layer insulation layer through a planarization process; performing a self-aligned etching (SAC) process selectively etching the inter-layer insulation layer, the second nitride layer and the oxide layer until the SAC etching process is stopped at the first nitride layer to thereby form a contact hole exposing the first nitride layer; and removing the first nitride layer by performing a blanket etch-back process to thereby expose the conductive layer.

Abstract: A method for fabricating a semiconductor device is capable of preventing a hard mask layer of a conductive structure from being damaged during a self-aligned contact etching process. The method includes the steps of: forming a plurality of conductive structures including a conductive layer and a hard mask layer on a substrate; sequentially forming a first nitride layer, an oxide layer, a second nitride layer, and an etch stop layer on the plurality of conductive structures; forming an inter-layer insulation layer on the etch stop layer; and performing a self-aligned contact (SAC) etching process selectively etching the inter-layer insulation layer, the etch stop layer, the second nitride layer and the oxide layer until the SAC etching process is stopped at the first nitride layer to thereby form a contact hole exposing the first nitride layer.

Abstract: A data latch circuit and method for improving operating speed therein may provide a reduction in delay time. The data latch circuit includes a sense amplifying unit outputting a first signal in response to input data, a first inverted signal in response to a clock signal, a second signal in response to given cascode data, and a second inverted signal in response to the clock signal. A clock latch unit may generate a gated clock signal to enable output of the given cascade data to the sense amplifying unit, in response to an enabling signal and the clock signal. A MUX unit outputs the first signal as output data and the first inverted signal as feedback data, or outputs the second signal as output data and second inverted signal as feedback data, based on the logic level of the enabling signal.

Abstract: A semiconductor device is disclosed that is capable of preventing a pattern collapse phenomenon in a cell edge area in which a pattern is more fragile. The semiconductor device has a lower pattern density in an edge area than in a central area of a wafer and includes a plurality of bar-type patterns allocated at a predetermined distance in the central area of the wafer; a plurality of dummy patterns formed in the edge area; and a plurality of a connection pattern for coupling at least two of the bar-type patterns to each other, wherein the connection patterns of the plurality of dummy patterns offset or staggered with respect to each other to form a disconnected zigzag pattern.

Abstract: Disclosed is a method for fabricating a semiconductor device having at least one contact holes formed by employing a self-aligned contact (SAC) etching process. The contact holes are formed through the shortened number of sequential steps by using different process recipes. First, an anti-reflective coating (ARC) layer formed on a substrate structure prepared sequentially with a substrate, conductive structures, an etch stop layer and an inter-layer insulation layer is etched by employing an etch gas of CF4, O2, CO and Ar. Then, a portion of an inter-layer insulation layer is etched with use of an etch gas of CF4 and O2. The rest portion of the inter-layer insulation layer is subsequently etched by using a different etch gas of C4F6, CH2F2, O2 and Ar to thereby form at least one contact hole exposing the etch stop layer.

Abstract: Disclosed is a method for fabricating a semiconductor device with protected conductive structures. The method includes the steps of: forming a plurality of conductive structures on a substrate, each conductive structure including a conductive layer and a hard mask insulation layer formed on the conductive layer; forming a first insulation layer on the conductive structures; forming a plurality of plugs contacted to the substrate disposed between the conductive structures by passing through the first insulation layer and having a predetermined height corresponding to a height between the conductive layer and a top of the hard mask insulation layer; forming an attack barrier layer covering top and sidewalls of the hard mask insulation layer; forming a second insulation layer on the attack barrier layer; and selectively etching the second insulation layer to form a contact hole exposing at least one of the plugs.