Abstract: A method for forming a contact hole in a semiconductor device is provided. A method for forming a contact hole in a semiconductor device includes: forming an insulation layer over a bottom structure; forming a hard mask pattern over the insulation layer; etching a portion of the insulation layer using the hard mask pattern as an etch mask to form an opening; forming spacers over sidewalls of the hard mask pattern and the insulation layer patterned by the etching; etching a remaining portion of the insulation layer to form a contact hole exposing a portion of the bottom structure; and removing the spacers and the hard mask pattern.

Abstract: A method for fabricating a three dimensional type capacitor is provided. The method includes forming a first insulation layer including first contact layers over a substrate, forming a second insulation layer over the first insulation layer, forming second contact layers by using a material having an etch selectivity different from the first contact layers such that the second contact layers are connected with the first contact layers within the second insulation layer, forming an etch stop layer over the second insulation layer and the second contact layers, forming a third insulation layer over the etch stop layer, etching the third insulation layer and the etch stop layer to form first contact holes exposing the second contact layers, etching the exposed second contact layers to form second contact holes exposing the first contact holes, and forming bottom electrodes over the inner surface of the second contact holes.

Abstract: Disclosed is a method for fabricating a semiconductor device without damaging a hard mask of a conductive structure. The method includes the steps of: forming a plurality of conductive structures on a substrate, each conductive structure including a conductive layer and a hard mask; sequentially forming a first nitride layer, an oxide layer, a second nitride layer, and an etch stop layer on the plurality of conductive structures; forming an inter-layer insulation layer on the etch stop layer; removing a portion of the inter-layer insulation layer through a planarization process; performing a self-aligned etching (SAC) process selectively etching the inter-layer insulation layer, the second nitride layer and the oxide layer until the SAC etching process is stopped at the first nitride layer to thereby form a contact hole exposing the first nitride layer; and removing the first nitride layer by performing a blanket etch-back process to thereby expose the conductive layer.

Abstract: A method for fabricating a transistor of a semiconductor device is provided. The method includes: forming device isolation layers in a substrate including a bottom structure, thereby defining an active region; etching the active region to a predetermined depth to form a plurality of recess structures each of which has a flat bottom portion with a critical dimension (CD) larger than that of a top portion; and sequentially forming a gate oxide layer and a metal layer on the recess structures; and patterning the gate oxide layer and the metal layer to form a plurality of gate structures.

Abstract: A method of etching is disclosed using a photoresist etch barrier formed by an exposure with a light source of which wavelength is in the range of 157 nm to 193 nm, such as an argon fluoride(ArF) laser or fluorine laser(F2 laser), the method includes the steps of coating a photoresist layer on a etch target layer; forming photoresist pattern by developing the photoresist layer after exposing the photoresist layer with a light source of which wavelength is in the range of 157 nm to 193 nm; forming a polymer layer and etching a portion of the etch target layer simultaneously with a mixture of fluorine-based gas, an Ar gas and an O2 gas, wherein the fluorine-based gas is CxFy or CaHbFc, and wherein x, y, a, b and c range from 1 to 10, respectively; and etching the etch target layer using the polymer layer and the photoresist pattern as the etch mask.

Abstract: Disclosed is a method for fabricating a semiconductor device with an improved process margin obtained by preventing damage to an inter-layer insulation layer during a wet cleaning process. Particularly, the method includes the steps of: forming a plurality of a first conductive pattern having a stack pattern of a first conductive and a first hard mask; forming a first inter-layer insulation layer of a good gap-fill property with a height between the first conductive material and the first hard mask on the first conductive layer; forming a second inter-layer insulation layer; forming a second conductive layer contacted the first conductive layer between the plurality of the first conductive patterns as passing through the first and the second inter-layer insulation layers; forming a third inter-layer insulation layer; forming a plurality of second conductive patterns; forming a fourth inter-layer insulation layer; and forming a third conductive layer contacted to the second conductive layer.

Abstract: A method for fabricating a semiconductor device capable of preventing a hard mask from being lifted and patterns from being defective. Particularly, an inter-layer insulation layer and an etch stop layer formed on a substrate structure provided with conductive structures are first planarized. Then, a hard mask made of a nitride-based material is formed by using a photoresist pattern and an anti-reflective coating layer as an etch mask. After the hard mask formation, the photoresist pattern and the anti-reflective coating layer are removed. Subsequently, a SAC etching process is performed to etch the inter-layer insulation layer with use of the hard mask as an etch mask, thereby obtaining a contact hole exposing the etch stop layer disposed between the conductive structures. The exposed etch stop layer is removed through the use of a blanket etch-back process, and a cleaning process is applied thereafter.

Abstract: A first insulation layer is formed on a substrate structure including an inter-layer insulation layer and a storage node contact plug. The first insulation layer is etched to form a first opening exposing a portion of the storage node contact plug. The first opening is filled with an organic polymer layer. An etch stop layer and a second insulation layer are formed on the organic polymer layer and the first insulation layer. A photoresist pattern is formed on the second insulation layer. The second insulation layer and the etch stop layer are etched to form a second opening exposing a portion of the organic polymer layer. The photoresist pattern and the organic polymer layer are removed, thereby extending a portion of the second opening. A storage node is formed over the extended second opening and the second insulation layer.

Abstract: A method for fabricating a semiconductor device is provided. The method includes: forming at least two gate patterns over a substrate; forming a first sidewall layer over on entire of the substrate structure including gat patterns; forming an insulation layer over the first sidewall layer; selectively removing the insulation layer between the gate patterns to form a contact hole partially exposing the first sidewall layer; forming a second sidewall layer over the first sidewall layer exposed by the contact hole; and removing the first and the second sidewall layers disposed at a bottom portion of the contact hole to expose a selected portion of the substrate between the gate patterns.

Abstract: The present invention relates to a method for fabricating a semiconductor device with a fine pattern. The method includes the steps of: (a) forming a semiconductor substrate structure including a substrate, a nitride layer for forming a hard mask, a plurality of conductive patterns, an etch stop layer, an inter-layer insulation layer, an anti-reflective coating (ARC) layer and a photoresist pattern; (b) selectively etching the ARC layer and the nitride layer with use of the photoresist pattern as an etch mask to form a hard mask; (c) removing the photoresist pattern and the ARC layer; (d) etching the inter-layer insulation layer disposed between the conductive patterns by using the hard mask as an etch mask to form a contact hole exposing the etch stop layer; (e) removing the etch stop layer formed at a bottom area of the contact hole to expose the substrate; and (f) forming a plug electrically contacted to the exposed substrate, wherein the steps (b) and (d) to (e) proceeds in an in situ condition.

Abstract: A semiconductor device capable of preventing a bridge generation during performing an etching process to form a plurality of gate structures on a substrate divided into an active region and a field region and an electrical short between a contact plug and the individual gate structure in the field region and a method for fabricating the same are provided. The semiconductor device includes: a substrate provided with an active region and a field region; a field oxide layer formed in the field region in such a way that the field oxide layer is recessed to be lower than a surface of the substrate disposed in the active region; and a plurality of gate structures formed on the field oxide layer and the substrate in the active region.

Abstract: A method for forming a capacitor in a semiconductor device comprises forming an inter-layer layer on a semi-finished substrate; etching the inter-layer insulation layer to form a plurality of first contact holes; forming a first insulation layer on sidewalls of the first contact holes; forming a plurality of storage-node contact plugs filled into the first contact holes; forming a second insulation layer with a different etch rate from the first insulation layer over the storage-node contact plugs; forming a third insulation layer on the second insulation layer; sequentially etching the third insulation layer and the second insulation layer to form a plurality of second contact holes exposing the storage-node contact plugs; and forming the storage node on each of the second contact holes.

Abstract: A method for fabricating a semiconductor device is provided. The method includes: preparing a substrate defined as active regions and inactive regions and provided with a plurality of conductive patterns; forming a buffer layer over the plurality of conductive patterns; forming an organic material having fluidity better than that of a photoresist layer on the buffer layer; flowing the organic material between the conductive patterns through a thermal treatment process, thereby filling a portion of each gap between the conductive patterns; forming the photoresist layer over the organic material and the buffer layer; forming a plurality of photoresist patterns opening the active regions through a photo-exposure process and a developing process; and performing an ion-implantation process using the plurality of photoresist patterns, thereby forming a plurality of junction regions in the active regions of the substrate.

Abstract: A method for fabricating a conducting layer pattern using a hard mask of which a upper surface is flattened by the use of ArF exposure light source.

Abstract: The present invention provides a method for fabricating a semiconductor device capable of decreasing a parasitic capacitance to thereby increase a cell capacitance. To achieve this effect, the deposited third inter-layer insulation layer is planarized and is subjected to a wet etching process to make its height lower than that of the bit line. Afterwards, the nitride-based etch stop layer is formed on the etched third inter-layer insulation layer, and then, the contact hole for forming the storage node contact plug is formed in between the bit lines through the SAC process so that the etch stop layer does not remain at sidewalls of the bit line. From this structure, it is possible to decrease the parasitic capacitance, and this decrease further provides an effect of increasing the cell capacitance.

Abstract: Disclosed is a method for fabricating a semiconductor device. The method includes: forming a first inter-layer insulation layer on a substrate provided with a plurality of cell contact plugs; selectively etching the first inter-layer insulation layer to form a plurality of first contact holes; performing a cleaning process to remove etch residues on lower portions of the first contact holes; forming insulating fences on inner walls of the first contact holes; forming a plurality of bit lines in contact with a group of the cell contact plugs through the respective first contact holes; forming a second inter-layer insulation layer over the plurality of bit lines; planarizing the second inter-layer insulation layer until an upper portion of each of the bit lines is exposed; and selectively etching the second inter-layer insulation layer in alignment with the bit lines, thereby obtaining a plurality of second contact holes.

Abstract: The present invention relates to a method for fabricating a semiconductor device with realizable advanced fine patterns.

Abstract: The present invention relates to a method for fabricating a semiconductor device using tungsten as a sacrificial hard mask material. The method includes the steps of: forming a layer on an etch target layer; forming a photoresist pattern on the layer; etching the layer by using the photoresist pattern as an etch mask along with use of a plasma containing CHF3 gas to form a sacrificial hard mask; and etching the etch target layer by using at least the sacrificial hard mask as an etch mask, thereby obtaining a predetermined pattern.

Abstract: The present invention relates to a method for fabricating a conducting layer pattern using a hard mask of which an upper surface is flattened by the use of ArF exposure light source. The method includes the steps of: forming a conducting layer on a semiconductor substrate; forming hard mask layers on the conducting layer; forming a photoresist pattern on the hard mask layers using an ArF exposure light source in order to form a predetermined pattern; forming a first hard mask pattern by etching a second hard mask layer using the photoresist pattern as an etching mask; etching a first hard mask layer and forming a second hard mask pattern, thereby forming a first resulting structure; depositing an insulation layer on the first resulting structure; and patterning the conducting layer using the second hard mask pattern as an etching mask.

Abstract: Disclosed is a method for fabricating a semiconductor device. The method includes the steps of: forming a plurality of conductive patterns on a substrate; depositing an insulation layer on the substrate; recessing the insulation layer until a vertical height of the insulation layer becomes lower than that of the plurality of conductive patterns; forming an etch stop layer in the form of sidewalls of the conductive patterns; forming a mask pattern over the etch stop layer; and forming a plurality of contact holes such that etch profiles of the plurality of contact holes are aligned with the plurality of conductive patterns and the substrate is exposed by etching the insulation layer by using the mask pattern as an etch mask.