Patents by Inventor Sung-min Hwang

Sung-min Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20180358372
    Abstract: A semiconductor memory device includes a cell array region and a peripheral circuit region. The cell array region includes an electrode structure including a plurality of electrodes sequentially stacked on a body conductive layer, and vertical structures penetrating the electrode structure so as to be connected to the body conductive layer. The peripheral circuit region includes a remaining substrate on the body conductive layer. The remaining substrate includes a buried insulating layer, and a peripheral active layer that is provided on the buried insulating layer and is substantially single-crystalline.
    Type: Application
    Filed: May 25, 2018
    Publication date: December 13, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min HWANG, Joon-Sung Lim, Gilsung Lee, Eunsuk Cho
  • SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20180358376
    Abstract: A semiconductor memory device includes a body conductive layer that includes a cell array portion and a peripheral circuit portion, an electrode structure on the cell array portion of the body conductive layer, vertical structures that penetrate the electrode structure, a residual substrate on the peripheral circuit portion of the body conductive layer, and a connection conductive pattern penetrating the residual substrate. The electrode structure includes a plurality of electrode that are stacked on top of each other. The vertical structures are connected to the cell array portion of the body conductive layer. The connection conductive pattern is connected to the peripheral circuit portion of the body conductive layer.
    Type: Application
    Filed: May 17, 2018
    Publication date: December 13, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min HWANG, Joon-Sung LIM, Jihye KIM
  • Vertical non-volatile memory device, method of fabricating the same device, and electric-electronic system having the same device
    Patent number: 10147739
    Abstract: Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: December 4, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Min Hwang, Han-Soo Kim, Won-Seok Cho, Jae-Hoon Jang
  • THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
    Publication number: 20180254247
    Abstract: A three-dimensional (3D) semiconductor device includes a substrate having a cell array region and a peripheral circuit region. A cell array structure is in the cell array region and includes a 3D memory cell array. A peripheral logic structure is in the peripheral circuit region and includes a peripheral circuit transistor. A cell insulating layer insulates the cell array structure. A peripheral insulating layer is insulated from the peripheral logic structure and the cell array region and has a porous layer.
    Type: Application
    Filed: November 27, 2017
    Publication date: September 6, 2018
    Inventors: Young-woo KIM, Joon-sung LIM, Jang-gn YUN, Sung-min Hwang
  • SEMICONDUCTOR MEMORY DEVICES INCLUDING A STRESS RELIEF REGION
    Publication number: 20180254284
    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a memory cell region and an insulator on a portion of the memory cell region. The semiconductor memory device includes a stress relief material that is in the insulator and is between the memory cell region and another region of the semiconductor memory device.
    Type: Application
    Filed: November 7, 2017
    Publication date: September 6, 2018
    Inventors: Sung-Min Hwang, Jang-Gn Yun, Joon-Sung Lim
  • Semiconductor Devices Including Resistors
    Publication number: 20180254271
    Abstract: A semiconductor device is provided including a resistor structure on a semiconductor substrate. The resistor structure includes pad portions and a resistor body connecting the pad portions. The pad portions each have a width greater than a width of the resistor body. The pad portions each include a pad pattern and a liner pattern covering a sidewall and a lower surface of the pad pattern. The resistor body extends laterally from the liner pattern. The pad pattern includes a different material from the resistor body and the liner pattern.
    Type: Application
    Filed: October 3, 2017
    Publication date: September 6, 2018
    Inventors: Hyo Seok Woo, Jang Gn YUN, Joon Sung LIM, Sung Min HWANG
  • VERTICAL MEMORY DEVICES
    Publication number: 20180247950
    Abstract: A vertical memory device includes a gate structure on a peripheral circuit region of a substrate, the substrate including a cell region and the peripheral circuit region, and the gate structure including a first gate electrode, second, third, and fourth gate electrodes sequentially disposed at a plurality of levels, respectively, on the cell region of the substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a first epitaxial layer extending through the second gate electrode on the cell region of the substrate, a channel extending through the third and fourth gate electrodes in the vertical direction on the first epitaxial layer, and a second epitaxial layer on a portion of the peripheral circuit region of the substrate adjacent the gate structure.
    Type: Application
    Filed: November 2, 2017
    Publication date: August 30, 2018
    Inventors: Su-Ok YUN, Jang-Gn YUN, Joon-Sung LIM, Sung-Min HWANG
  • Vertical non-volatile memory device and method of fabricating the same
    Patent number: 9966115
    Abstract: A vertical non-volatile memory device includes a substrate, and a first stack of word lines and a second stack of word lines extending in a first direction on the substrate and separated from each other in a second direction perpendicular to the first direction. The device further includes first array lines extending in the second direction on the first and the second stack, and connected to word lines of the first and the second stack through at least two of first via contacts in a same level. The device further include first word select lines being in a same level and extending in the first direction, and connected to each of the first array lines through at least one of second via contacts. Ends of each of the first and the second stack have a form of stairs on the substrate.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: May 8, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Hwang, Han-Soo Kim, Won-Seok Cho, Jae-Hoon Jang, Sun-Il Shim, Jae-Hun Jeong, Ki-Hyun Kim
  • Vertical memory devices having contact plugs contacting stacked gate electrodes
    Patent number: 9899394
    Abstract: A vertical memory device includes a plurality of gate electrodes at a plurality of levels, respectively, spaced apart from each other in a vertical direction substantially perpendicular to a top surface of a substrate, a channel extending in the vertical direction on the substrate and penetrating through the gate electrodes, and a plurality of contact plugs extending in the vertical direction and contacting the gate electrodes, respectively. At least one second contact plug is formed on a first gate electrode among the plurality of gate electrodes, and extends in the vertical direction.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: February 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Hwang, Jee-Yong Kim, Dae-Seok Byeon
  • Vertical non-volatile memory device, method of fabricating the same device, and electric-electronic system having the same device
    Patent number: 9881934
    Abstract: Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: January 30, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-min Hwang, Han-soo Kim, Won-seok Cho, Jae-hoon Jang
  • Semiconductor devices including a conductive pattern contacting a channel pattern and methods of manufacturing the same
    Patent number: 9859296
    Abstract: A semiconductor device includes a plurality of insulation patterns and a plurality of gates alternately and repeatedly stacked on a substrate, a channel pattern extending through the gates in a first direction substantially perpendicular to a top surface of the substrate, a semiconductor pattern between the channel pattern and the substrate, and a conductive pattern between the channel pattern and the semiconductor pattern. The conductive pattern electrically connects the channel pattern to the semiconductor pattern. The conductive pattern contacts a bottom edge of the channel pattern and an upper surface of the semiconductor pattern.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: January 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se-Jun Park, Jang-Gn Yun, Sung-Min Hwang, Ahn-Sik Moon, Zhiliang Xia
  • Semiconductor device having channel holes
    Patent number: 9853045
    Abstract: A semiconductor device includes a gate stack including gate electrodes stacked vertically on a substrate. Channel holes penetrate through the gate stack to extend vertically to the substrate. Each of the channel holes includes a channel region. First channel pads are each disposed at an end of a respective channel hole opposite the substrate. Each of the first channel pads includes at least one first conductivity-type impurity. Second channel pads are each disposed at an end of a respective channel hole opposite the substrate. Each of the second channel pads includes at least one second conductivity-type impurity.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: December 26, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Min Hwang, Jang Gn Yun, Ahn Sik Moon, Se Jun Park, Zhiliang Xia, Joon Sung Lim
  • VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    Publication number: 20170365612
    Abstract: A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.
    Type: Application
    Filed: August 31, 2017
    Publication date: December 21, 2017
    Inventors: Jang-Gn YUN, Zhiliang XIA, Ahn-Sik Moon, Se-Jun PARK, Joon-Sung LIM, Sung-Min HWANG
  • THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
    Publication number: 20170338242
    Abstract: A three-dimensional semiconductor device may include a lower electrode structure having a plurality of lower electrodes vertically stacked on a substrate and an upper electrode structure having a plurality of upper electrodes stacked on the lower electrode structure. Each of the lower and upper electrodes may include an electrode portion that is parallel to a top surface of the substrate and a vertical pad portion that is inclined with respect to the top surface of the substrate. The vertical pad portions of adjacent lower electrodes may be spaced apart from each other by a first horizontal distance. The vertical pad portions of adjacent lower and upper electrodes may be spaced apart from each other by a second horizontal distance that is greater than the first horizontal distance.
    Type: Application
    Filed: February 20, 2017
    Publication date: November 23, 2017
    Inventor: Sung-Min HWANG
  • Three-dimensional semiconductor device
    Patent number: 9812464
    Abstract: A three-dimensional semiconductor device may include a lower electrode structure having a plurality of lower electrodes vertically stacked on a substrate and an upper electrode structure having a plurality of upper electrodes stacked on the lower electrode structure. Each of the lower and upper electrodes may include an electrode portion that is parallel to a top surface of the substrate and a vertical pad portion that is inclined with respect to the top surface of the substrate. The vertical pad portions of adjacent lower electrodes may be spaced apart from each other by a first horizontal distance. The vertical pad portions of adjacent lower and upper electrodes may be spaced apart from each other by a second horizontal distance that is greater than the first horizontal distance.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: November 7, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sung-Min Hwang
  • THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20170309639
    Abstract: An electrode structure includes a plurality of electrodes vertically stacked on a substrate. Each of the plurality of electrodes includes an electrode portion, a pad portion and a protrusion. The electrode portion is parallel to a top surface of the substrate, extending in a first direction. The pad portion extends from the electrode portion in an inclined direction with respect to the top surface of the substrate. The protrusion protrudes from a portion of the pad portion in a direction parallel to the inclined direction. Protrusions of the plurality of electrodes are arranged in a direction diagonal to the first direction when viewed from a plan view.
    Type: Application
    Filed: March 16, 2017
    Publication date: October 26, 2017
    Inventors: SUNG-MIN HWANG, SUNGHOI HUR
  • Vertical memory devices and methods of manufacturing the same
    Patent number: 9786676
    Abstract: A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: October 10, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jang-Gn Yun, Zhiliang Xia, Ahn-Sik Moon, Se-Jun Park, Joon-Sung Lim, Sung-Min Hwang
  • VERTICAL NON-VOLATILE MEMORY DEVICE, METHOD OF FABRICATING THE SAME DEVICE, AND ELECTRIC-ELECTRONIC SYSTEM HAVING THE SAME DEVICE
    Publication number: 20170243885
    Abstract: Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.
    Type: Application
    Filed: May 10, 2017
    Publication date: August 24, 2017
    Inventors: SUNG-MIN HWANG, Han-Soo Kim, Won-Seok Cho, Jae-Hoon Jang
  • VERTICAL NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    Publication number: 20170236559
    Abstract: A vertical non-volatile memory device includes a substrate, and a first stack of word lines and a second stack of word lines extending in a first direction on the substrate and separated from each other in a second direction perpendicular to the first direction. The device further includes first array lines extending in the second direction on the first and the second stack, and connected to word lines of the first and the second stack through at least two of first via contacts in a same level. The device further include first word select lines being in a same level and extending in the first direction, and connected to each of the first array lines through at least one of second via contacts. Ends of each of the first and the second stack have a form of stairs on the substrate.
    Type: Application
    Filed: May 3, 2017
    Publication date: August 17, 2017
    Inventors: SUNG-MIN HWANG, HAN-SOO KIM, WON-SEOK CHO, JAE-HOON JANG, SUN-IL SHIM, JAE-HUN JEONG, KI-HYUN KIM
  • Vertical non-volatile memory device including plural word line stacks
    Patent number: 9711188
    Abstract: A vertical non-volatile memory device includes a substrate, and a first stack of word lines and a second stack of word lines extending in a first direction on the substrate and separated from each other in a second direction perpendicular to the first direction. The device further includes first array lines extending in the second direction on the first and the second stack, and connected to word lines of the first and the second stack through at least two of first via contacts in a same level. The device further include first word select lines being in a same level and extending in the first direction, and connected to each of the first array lines through at least one of second via contacts. Ends of each of the first and the second stack have a form of stairs on the substrate.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: July 18, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Hwang, Han-Soo Kim, Won-Seok Cho, Jae-Hoon Jang, Sun-Il Shim, Jae-Hun Jeong, Ki-Hyun Kim