Abstract: A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.

Abstract: A semiconductor device includes a plurality of insulation patterns and a plurality of gates alternately and repeatedly stacked on a substrate, a channel pattern extending through the gates in a first direction substantially perpendicular to a top surface of the substrate, a semiconductor pattern between the channel pattern and the substrate, and a conductive pattern between the channel pattern and the semiconductor pattern. The conductive pattern electrically connects the channel pattern to the semiconductor pattern. The conductive pattern contacts a bottom edge of the channel pattern and an upper surface of the semiconductor pattern.

Abstract: A semiconductor device includes a gate stack including gate electrodes stacked vertically on a substrate. Channel holes penetrate through the gate stack to extend vertically to the substrate. Each of the channel holes includes a channel region. First channel pads are each disposed at an end of a respective channel hole opposite the substrate. Each of the first channel pads includes at least one first conductivity-type impurity. Second channel pads are each disposed at an end of a respective channel hole opposite the substrate. Each of the second channel pads includes at least one second conductivity-type impurity.

Abstract: Step shape pad structure and wiring structure in vertical type semiconductor device are include a first conductive line having a first line shape and including first pad regions at an upper surface of an edge portion, and a second conductive line having s second line shape and being spaced apart from the first conductive line and provided on the first conductive line. An end portion of the first conductive line is extended to a first position. Second pad regions are included on an upper surface of an edge portion of the second conductive line. An end portion of the second conductive line is extended to the first position. The second conductive line includes a dent portion at a facing portion to the first pad regions in a vertical direction to expose the first pad regions. The pad structure may be used in a vertical type nonvolatile memory device.

Abstract: Disclosed herein is a folding device to manufacture a stacked/folded type electrode assembly having unit cells sequentially stacked in a state in which a separation film is disposed between the respective unit cells, the folding device including a web supply unit to supply a web having plate-shaped unit cells arranged at a top of a separation film at predetermined intervals, a winding jig to rotate the unit cells while holding a first one of the unit cells of the web so that the unit cells are sequentially stacked in a state in which the separation film is disposed between the respective unit cells, and a rotary shaft compensation unit to compensate for the position of a rotary shaft of the winding jig in an advancing direction of the web (X-axis direction).

Abstract: A vertical memory device includes a plurality of gate electrodes at a plurality of levels, respectively, spaced apart from each other in a vertical direction substantially perpendicular to a top surface of a substrate, a channel extending in the vertical direction on the substrate and penetrating through the gate electrodes, and a plurality of contact plugs extending in the vertical direction and contacting the gate electrodes, respectively. At least one second contact plug is formed on a first gate electrode among the plurality of gate electrodes, and extends in the vertical direction.

Abstract: A semiconductor device includes bit lines on a substrate, a gate structure provided between the substrate and the bit lines, a common source line provided between the gate structure and the bit lines, and channel structures connecting the bit lines to the common source line. Each of the channel structures may include a plurality of first vertical portions penetrating the gate structure and being connected to the bit lines, a second vertical portion penetrating the gate structure and being connected to the common source line, and a horizontal portion provided between the substrate and the gate structure to connect the first and second vertical portions to each other.

Abstract: A vertical non-volatile memory device is structured/fabricated to include a substrate, groups of memory cell strings each having a plurality of memory transistors distributed vertically so that the memory throughout multiple layers on the substrate, integrated word lines coupled to sets of the memory transistors, respectively, and stacks of word select lines. The memory transistors of each set are those transistors, of one group of the memory cell strings, which are disposed in the same layer above the substrate. The word select lines are respectively connected to the integrated word lines.

Abstract: A vertical structure non-volatile memory device includes semiconductor regions that vertically extend on a substrate, a plurality of memory cell strings that vertically extend on the substrate along sidewalls of the semiconductor regions and include a plurality of memory cells and at least one or more first selection transistors, which are disposed on sides of the memory cells and are adjacent to one another. A plurality of wordlines is connected to the memory cells of the memory cell strings. A first selection line is connected to the selection transistors of the memory cell strings and insulating regions are formed as air gaps between the first selection transistors of the adjacent memory cell strings.

Abstract: A semiconductor memory device includes: a semiconductor region extending vertically from a first region of a substrate; a plurality of gate electrodes disposed on the first region of the substrate in a vertical direction, but separated from each other along a sidewall of the semiconductor region; a gate dielectric layer disposed between the semiconductor region and the plurality of gate electrodes; a substrate contact electrode extending vertically from the impurity-doped second region of the substrate; and an insulating region formed as an air gap between the substrate contact electrode and at least one of the plurality of gate electrodes.

Abstract: A light emitting device is described, including a second conductive type semiconductor layer; an active layer over the second conductive type semiconductor layer; a first conductive type semiconductor layer over the active layer; a second electrode in a first region under the second conductive type semiconductor layer; a current blocking layer including a metal; and a first electrode over the first conductive type semiconductor layer. Further, the first electrode has at least one portion that vertically overlaps the current blocking layer.

Abstract: A semiconductor memory device includes: a semiconductor region extending vertically from a first region of a substrate; a plurality of gate electrodes disposed on the first region of the substrate in a vertical direction, but separated from each other along a sidewall of the semiconductor region; a gate dielectric layer disposed between the semiconductor region and the plurality of gate electrodes; a substrate contact electrode extending vertically from the impurity-doped second region of the substrate; and an insulating region formed as an air gap between the substrate contact electrode and at least one of the plurality of gate electrodes.

Abstract: Disclosed herein is a light emitting device exhibiting improved current spreading. The disclosed light emitting device includes a light emitting structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer disposed between the first conductivity type and second conductivity type semiconductor layers, a first electrode disposed on the first conductivity type semiconductor layer, and a second electrode disposed on the second conductivity type semiconductor layer. The light emitting structure includes a mesa etching region where the second conductivity type semiconductor layer, active layer, and first conductivity type semiconductor layer are partially etched, thereby exposing a portion of the first conductivity type semiconductor layer. The first electrode is disposed on the exposed portion of the first conductivity type semiconductor layer.

Abstract: A vertical type semiconductor device includes first and second word line structures that include first and second word lines. The word lines surround a plurality of pillar structures, which are provided to connect the word lines to corresponding string select lines. Connecting patterns electrically connect pairs of adjacent first and second word lines in a same plane. The device may be a nonvolatile memory device or a different type of device.

Abstract: A method of manufacturing a vertical type memory device includes stacking a first lower insulating layer, one layer of a lower sacrificial layer and a second lower insulating layer on a substrate, forming a stacking structure by stacking sacrificial layers and insulating layers, and etching an edge portion of the stacking structure to form a preliminary stepped shape pattern structure. The preliminary stepped shape pattern structure has a stepped shape edge portion. A pillar structure making contact with a surface of the substrate is formed. The preliminary stepped shape pattern structure, the lower sacrificial layer, and the first and second lower insulating layers are partially etched to form a first opening portion and a second opening portion to form a stepped shape pattern structure. The second opening portion cuts at least an edge portion of the lower sacrificial layer.

Abstract: Embodiments relate to a light emitting device, a light emitting device package, and a lighting system including the same. The light emitting device includes a light emitting structure, a second electrode under the light emitting structure and an insulating layer disposed on the at least one of the protrusions. The second electrode includes a bottom member and at least one of protrusions on the bottom member that penetrates the second conductive type semiconductor layer and the active layer. The at least one of the protrusions includes an upper portion and a lower portion having different size.

Abstract: Disclosed herein is a light emitting device exhibiting improved current spreading. The disclosed light emitting device includes a light emitting structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer disposed between the first conductivity type and second conductivity type semiconductor layers, a first electrode disposed on the first conductivity type semiconductor layer, and a second electrode disposed on the second conductivity type semiconductor layer. The light emitting structure includes a mesa etching region where the second conductivity type semiconductor layer, active layer, and first conductivity type semiconductor layer are partially etched, thereby exposing a portion of the first conductivity type semiconductor layer. The first electrode is disposed on the exposed portion of the first conductivity type semiconductor layer.

Abstract: Disclosed herein is a folding device to manufacture a stacked/folded type electrode assembly having unit cells sequentially stacked in a state in which a separation film is disposed between the respective unit cells, the folding device including a web supply unit to supply a web having plate-shaped unit cells arranged at the top of a separation film at predetermined intervals, a winding jig to rotate the unit cells while holding a first one of the unit cells of the web so that the unit cells are sequentially stacked in a state in which the separation film is disposed between the respective unit cells, and a Y-axis directional rotary shaft compensation unit to compensate for a position of a rotary shaft of the winding jig in a direction (Y-axis direction) perpendicular to an advancing direction of the web, wherein the Y-axis directional rotary shaft compensation unit periodically changes the position of the rotary shaft in the direction (Y axis) perpendicular to the advancing direction (X axis) of the web to m

Abstract: A semiconductor device includes bit lines on a substrate, a gate structure provided between the substrate and the bit lines, a common source line provided between the gate structure and the bit lines, and channel structures connecting the bit lines to the common source line. Each of the channel structures may include a plurality of first vertical portions penetrating the gate structure and being connected to the bit lines, a second vertical portion penetrating the gate structure and being connected to the common source line, and a horizontal portion provided between the substrate and the gate structure to connect the first and second vertical portions to each other.

Abstract: The disclosure relates to an m-plane substrate, a growth inhibitor region located on the m-plane substrate, the growth inhibitor region having a plurality of windows for growing a III-nitride semiconductor, a seed layer formed at least at regions corresponding to the plurality of windows on the m-plane substrate, and a III-nitride semiconductor layer grown from the seed layer and coalesced after propagated along a-axis and c-axis directions.