Abstract: A three-dimensional semiconductor device includes first and second selection lines stacked one on the other. An upper line horizontally crosses over the first and second selection lines. First and second vertical patterns vertically cross the first and second selection lines. The first and second vertical patterns are connected in common to the upper line. Each of the first and second vertical patterns constitutes first and second selection transistors that are connected in series to each other. The first selection transistors of the first and second vertical patterns are controlled by the first and second selection lines, respectively.

Abstract: Disclosed is a method for manufacturing a battery cell including an electrode assembly and electrolyte provided in a battery case made of a laminate sheet having a resin layer and a metal layer, which includes: (a) mounting the electrode assembly in the battery case and sealing the periphery of the battery case except for one end part thereof through thermal fusion; (b) introducing the electrolyte through the unsealed end part and sealing the end via thermal fusion; (c) charging-discharging the battery cell to activate the same; (d) transferring gas generated during activation and excess electrolyte to the foregoing end part of the battery cell by centrifugal force; and (e) removing the gas and excess electrolyte from the end part.

Abstract: Provided is a semiconductor device that includes first and second isolation patterns disposed on a substrate. Alternately stacked interlayer insulating patterns and a conductive patterns are disposed on a surface of the substrate between the first and second isolation patterns. A support pattern penetrates the conductive patterns and the interlayer insulating patterns and has a smaller width than the first and second isolation patterns. First and second vertical structures are disposed between the first isolation and the support pattern and penetrate the conductive patterns and the interlayer insulating patterns. A second vertical structure is disposed between the second isolation pattern and the support pattern and penetrates the conductive patterns and the interlayer insulating patterns. A distance between top and bottom surfaces of the support pattern is greater than a distance between a bottom surface of the support pattern and the surface of the substrate.

Abstract: A semiconductor memory device includes: a semiconductor region extending vertically from a first region of a substrate; a plurality of gate electrodes disposed on the first region of the substrate in a vertical direction, but separated from each other along a sidewall of the semiconductor region; a gate dielectric layer disposed between the semiconductor region and the plurality of gate electrodes; a substrate contact electrode extending vertically from the impurity-doped second region of the substrate; and an insulating region formed as an air gap between the substrate contact electrode and at least one of the plurality of gate electrodes.

Abstract: Disclosed herein is a light emitting device exhibiting improved current spreading. The disclosed light emitting device includes a light emitting structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer disposed between the first conductivity type and second conductivity type semiconductor layers, a first electrode disposed on the first conductivity type semiconductor layer, and a second electrode disposed on the second conductivity type semiconductor layer. The light emitting structure includes a mesa etching region where the second conductivity type semiconductor layer, active layer, and first conductivity type semiconductor layer are partially etched, thereby exposing a portion of the first conductivity type semiconductor layer. The first electrode is disposed on the exposed portion of the first conductivity type semiconductor layer.

Abstract: A three-dimensional semiconductor device includes a substrate having a cell array region between first and second contact regions. A first stack includes a plurality of first electrodes vertically provided on the substrate, and a second stack includes a plurality of second electrodes vertically provided on the first stack. The second stack is arranged to expose end portions of the first electrodes on the first contact region and overlap end portions of the first electrodes on the second contact region.

Abstract: A method of manufacturing a vertical type memory device includes stacking a first lower insulating layer, one layer of a lower sacrificial layer and a second lower insulating layer on a substrate, forming a stacking structure by stacking sacrificial layers and insulating layers, and etching an edge portion of the stacking structure to form a preliminary stepped shape pattern structure. The preliminary stepped shape pattern structure has a stepped shape edge portion. A pillar structure making contact with a surface of the substrate is formed. The preliminary stepped shape pattern structure, the lower sacrificial layer, and the first and second lower insulating layers are partially etched to form a first opening portion and a second opening portion to form a stepped shape pattern structure. The second opening portion cuts at least an edge portion of the lower sacrificial layer.

Abstract: Disclosed is a device for notching, at an interval of a unit electrode, a continuous electrode sheet in which an electrode active material is applied to one or both surfaces thereof, to form a plurality of unit electrodes from the electrode sheet, the device including a press to press notches on the top and the bottom of the electrode sheet at a set position, and a drawing member arranged at the rear of the press based on a feed direction of the electrode sheet, the drawing member drawing and transporting the electrode sheet by one pitch, a size corresponding to the unit electrode according to operation of the press, wherein, when one of the grippers draws and transports the electrode sheet, the remaining grippers move to a position for drawing.

Abstract: A light emitting device including a light emitting structure having a first conductive semiconductor layer, an active layer disposed under the active layer and a second conductive semiconductor layer disposed under the active layer; a trench formed in a portion of the light emitting structure; a current barrier layer in the trench and configured to hinder current supply to the active layer at a portion where the trench is located and to block the active layer over the trench from emitting light; and a first electrode on the first conductive semiconductor layer above the portion where the trench is located.

Abstract: A vertical structure non-volatile memory device includes semiconductor regions that vertically extend on a substrate, a plurality of memory cell strings that vertically extend on the substrate along sidewalls of the semiconductor regions and include a plurality of memory cells and at least one or more first selection transistors, which are disposed on sides of the memory cells and are adjacent to one another. A plurality of wordlines is connected to the memory cells of the memory cell strings. A first selection line is connected to the selection transistors of the memory cell strings and insulating regions are formed as air gaps between the first selection transistors of the adjacent memory cell strings.

Abstract: Disclosed herein is an electrode assembly of a cathode/separator/anode structure, wherein a plurality of first unit electrodes and a second electrode sheet are wound so that the first unit electrodes are opposite to the second electrode sheet via a separator sheet, and a first electrode and a second electrode have opposite polarities.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate doped with a first conductive type dopant, a plurality of stacked structures arranged side by side on the substrate and extending in a first direction, each of the stacked structures including gate electrodes spaced apart from each other, the plurality of stacked structures including a pair of stacked structures spaced apart from each other at a first interval in a second direction perpendicular to the first direction, and a pick-up region extending in the first direction in the substrate between the pair of stacked structures and doped with the first conductive type dopant.

Abstract: Disclosed is a device for cutting an electrode sheet laminate wherein two or more continuous electrode sheets, in which an electrode active material is applied to one or both surfaces thereof, are laminated, to form a plurality of unit electrode laminates from the electrode sheet laminate, the device including a cutter to cut the electrode sheet laminate at a set position and thereby form unit electrode laminates, and two or more transport grippers arranged at the front of the cutter based on a feed direction of the electrode sheet laminate, the transport grippers drawing and transporting the electrode sheet laminate by one pitch, a size corresponding to the unit electrode laminate according to operation of the cutter, wherein while one of the transport grippers draws and transports the electrode sheet laminate, the remaining transport grippers move to a position for drawing.

Abstract: A method of manufacturing a vertical type memory device includes stacking a first lower insulating layer, one layer of a lower sacrificial layer and a second lower insulating layer on a substrate, forming a stacking structure by stacking sacrificial layers and insulating layers, and etching an edge portion of the stacking structure to form a preliminary stepped shape pattern structure. The preliminary stepped shape pattern structure has a stepped shape edge portion. A pillar structure making contact with a surface of the substrate is formed. The preliminary stepped shape pattern structure, the lower sacrificial layer, and the first and second lower insulating layers are partially etched to form a first opening portion and a second opening portion to form a stepped shape pattern structure. The second opening portion cuts at least an edge portion of the lower sacrificial layer.

Abstract: A vertical structure non-volatile memory device includes semiconductor regions that vertically extend on a substrate, a plurality of memory cell strings that vertically extend on the substrate along sidewalls of the semiconductor regions and include a plurality of memory cells and at least one or more first selection transistors, which are disposed on sides of the memory cells and are adjacent to one another. A plurality of wordlines is connected to the memory cells of the memory cell strings. A first selection line is connected to the selection transistors of the memory cell strings and insulating regions are formed as air gaps between the first selection transistors of the adjacent memory cell strings.

Abstract: Disclosed herein is a battery cell manufacturing device configured to manufacture a battery cell including two or more unit cells. The battery cell manufacturing device includes a unit cell stacking unit into which unit cells are introduced from above and in which the unit cells are sequentially stacked, a wrapping unit to wrap an outside of the unit cell stack discharged from the unit cell stacking unit with a separation film, and a heating unit to thermally shrink the separation film wrapping the outside of the unit cell stack.

Abstract: A three dimensional semiconductor memory device has a stacked structure including cell gates stacked therein that are insulated from each other and first string selection gates laterally separated from each other, vertical active patterns extending through the first string selection gates, multi-layered dielectric layers between sidewalls of the vertical active patterns and the cell gates and between the sidewalls of the vertical active patterns and the first string selection gates, and at least one first supplement conductive pattern. The first string selection gates are disposed over an uppermost cell gate of the cell gates. Each vertical active pattern extends through each of the cell gates stacked under the first string selection gates. The first supplement conductive pattern is in contact with a sidewall of one of the first string selection gates.

Abstract: Disclosed is a packing structure for a lithium ion polymer battery, which includes: a battery casing including a lower multilayer polymer and an upper multilayer polymer, wherein the lower multilayer polymer has an inner space of a predetermined size for housing at least one electrode assembly and an electrolyte and is provided with an extension portion extending radially and outwardly from a top edge of each vertical portion of the lower multilayer polymer, a part of the upper multilayer polymer is coupled rotatably to a part of the extension portion of the lower multilayer polymer and remaining parts of the upper multilayer polymer are sealed to remaining parts of the extension portion of the lower multilayer polymer; and a battery protection member, which wraps the outer circumference of the battery casing so that the battery contained in the battery casing can be protected from external impact, and is fixed integrally by a part of the sealed extension portions.

Abstract: Disclosed is a method for manufacturing a battery cell including an electrode assembly and electrolyte provided in a battery case composed of a laminate sheet having a resin layer and a metal layer, which includes; (a) thermally fusing and sealing the periphery of the case except for an end part thereof while the electrode assembly is mounted in the case; (b) introducing the electrolyte through the unsealed end part then sealing the same by thermal fusion; (c) charging and discharging the battery cell to activate the same; (d) puncturing the unsealed part inside the end part to form a through-hole communicating with the inside of the case; and (e) pulling top and bottom faces of the battery case in the opposite direction to each other at the unsealed part to open the same while applying vacuum pressure, to thereby remove the gas generated during activation as well as excess electrolyte.

Abstract: A light emitting device is described, including a second conductive type semiconductor layer; an active layer over the second conductive type semiconductor layer; a first conductive type semiconductor layer over the active layer; a second electrode in a first region under the second conductive type semiconductor layer; a current blocking layer including a metal; and a first electrode over the first conductive type semiconductor layer. Further, the first electrode has at least one portion that vertically overlaps the current blocking layer.