Patents by Inventor Sung Min Yoon
Sung Min Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11342344Abstract: The present disclosure relates to a memory device, and more particularly, to a memory device including a substrate, a plurality of vertical structures disposed on the substrate and including insulation layers and lower electrodes, which are alternately laminated with each other, wherein the vertical structures are aligned in a first direction parallel to a top surface of the substrate and a second direction crossing the first direction, an upper electrode disposed on a top surface and side surfaces of each of the vertical structures, and a first dielectric layer disposed between the upper electrode and the vertical structures to cover the top surface and the side surfaces of each of the vertical structures. Here, the first dielectric layer includes a ferroelectric material.Type: GrantFiled: November 4, 2020Date of Patent: May 24, 2022Assignees: Electronics and Telecommunications Research Institute, University-Industry Cooperation Group of Kyung Hee UniversityInventors: Seungeon Moon, Bae Ho Park, Sung-Min Yoon, Seung Youl Kang, Jeong Hun Kim, Jiyong Woo, Jong Pil Im, Chansoo Yoon, Ji Hoon Jeon
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Publication number: 20210134813Abstract: The present disclosure relates to a memory device, and more particularly, to a memory device including a substrate, a plurality of vertical structures disposed on the substrate and including insulation layers and lower electrodes, which are alternately laminated with each other, wherein the vertical structures are aligned in a first direction parallel to a top surface of the substrate and a second direction crossing the first direction, an upper electrode disposed on a top surface and side surfaces of each of the vertical structures, and a first dielectric layer disposed between the upper electrode and the vertical structures to cover the top surface and the side surfaces of each of the vertical structures. Here, the first dielectric layer includes a ferroelectric material.Type: ApplicationFiled: November 4, 2020Publication date: May 6, 2021Applicants: Electronics and Telecommunications Research Institute, University-Industry Cooperation Group of Kyung Hee UniversityInventors: Seungeon MOON, Bae Ho PARK, Sung-Min YOON, Seung Youl KANG, Jeong Hun KIM, Jiyong WOO, Jong Pil IM, Chansoo YOON, Ji Hoon JEON
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Patent number: 10552494Abstract: A content providing method of a content providing system is provided. The method includes transmitting identification information in a broadcasting manner from a first electronic device, if the identification information is received, generating user history information based on a receiving record of the identification information, at a second electronic device, transmitting the user history information to a database server from the second electronic device, transmitting the user history information to the first electronic device from the database server, transmitting the user history information to a content server at the first electronic device, transmitting a content associated with the user history information to the first electronic device from the content server, and providing the content to a user of the first electronic device.Type: GrantFiled: March 2, 2016Date of Patent: February 4, 2020Assignee: Samsung Electronics Co., LtdInventors: Chang Hyup Jwa, Kyung Tae Kim, Jung Jik Lee, Sung Min Yoon, Sun Kee Lee
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Patent number: 10008155Abstract: Provided is a gate driving circuit. The gate driving circuit includes an ith modulation circuit and an ith line selection circuit (where i is a natural number greater than 1). The ith modulation circuit outputs an ith modulation voltage to an ith line selection circuit based on received first to third control signals. The ith line selection circuit includes a memory transistor that is turned on or turned off according to a level of the received ith modulation voltage.Type: GrantFiled: July 27, 2016Date of Patent: June 26, 2018Assignees: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, UNIVERSITY-INDUSTRY COOPERATION GROUP OF KYUNG HEE UNIVInventors: Chunwon Byun, Jong-Heon Yang, Sung-Min Yoon, Kyoung Ik Cho, Chi-Sun Hwang
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Publication number: 20180176536Abstract: An electronic device is provided that includes a display displaying an image and a processor electrically connected with the display. The processor is configured to vary a start position of projection, where the image is played based on a resolution of the display and a resolution of the image, and to resize and display a portion of the image which is displayed on the display.Type: ApplicationFiled: December 19, 2017Publication date: June 21, 2018Inventors: Han-Sol JO, Kyung-Tae Kim, Keon-Ho Kim, Sung-Min Yoon, Seon-Ho Lee, Chang-Ho Lee, Sun-Goo Jung, Ji-Hoon Chung, Yoon-Jeong Choi, Ho-Seon Lee, Jae-Seong Hwang
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Publication number: 20170161240Abstract: An electronic device is provided.Type: ApplicationFiled: December 6, 2016Publication date: June 8, 2017Inventors: Jung Jik LEE, Kyung Tae KIM, Yoon Jeong CHOI, Hye Rim BAE, Sung Min YOON, Chang Hyup JWA, Chang Ho LEE
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Publication number: 20170032741Abstract: Provided is a gate driving circuit. The gate driving circuit includes an ith modulation circuit and an ith line selection circuit (where i is a natural number greater than 1). The ith modulation circuit outputs an ith modulation voltage to an ith line selection circuit based on received first to third control signals. The ith line selection circuit includes a memory transistor that is turned on or turned off according to a level of the received ith modulation voltage.Type: ApplicationFiled: July 27, 2016Publication date: February 2, 2017Inventors: Chunwon BYUN, Jong-Heon YANG, Sung-Min YOON, Kyoung Ik CHO, Chi-Sun HWANG
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Publication number: 20160259855Abstract: A content providing method of a content providing system is provided. The method includes transmitting identification information in a broadcasting manner from a first electronic device, if the identification information is received, generating user history information based on a receiving record of the identification information, at a second electronic device, transmitting the user history information to a database server from the second electronic device, transmitting the user history information to the first electronic device from the database server, transmitting the user history information to a content server at the first electronic device, transmitting a content associated with the user history information to the first electronic device from the content server, and providing the content to a user of the first electronic device.Type: ApplicationFiled: March 2, 2016Publication date: September 8, 2016Inventors: Chang Hyup JWA, Kyung Tae KIM, Jung Jik LEE, Sung Min YOON, Sun Kee LEE
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Patent number: 9099991Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.Type: GrantFiled: October 9, 2013Date of Patent: August 4, 2015Assignees: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, KONKUK UNIVERSITY INDUSTRIAL COOPERATION CORP.Inventors: Sang Hee Park, Chi Sun Hwang, Sung Min Yoon, Him Chan Oh, Kee Chan Park, Tao Ren, Hong Kyung Leem, Min Woo Oh, Ji Sun Kim, Jae Eun Pi, Byeong Hoon Kim, Byoung Gon Yu
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Patent number: 8901532Abstract: Provided is a non-volatile programmable device including a first terminal, a first threshold switching layer connected to part of the first terminal, a phase change layer connected to the first threshold switching layer, a second threshold switching layer connected to the phase change layer, a second terminal connected to the second threshold switching layer, and third and fourth terminals respectively connected to a side portion of the phase change layer and the other side portion opposite to the side portion of the phase change layer.Type: GrantFiled: May 8, 2012Date of Patent: December 2, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Seung Yun Lee, Young Sam Park, Sung Min Yoon, Soonwon Jung, Sang Hoon Cheon, Byoung Gon Yu
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Patent number: 8872146Abstract: Provided are a Phase-change Random Access Memory (PRAM) device and a method of manufacturing the same. In particular, a PRAM device including a heating layer, wherein the heating layer comprises first and second heating layers having different physical properties from each other and a method of manufacturing the same are provided. Since the PRAM device according to the present invention includes a heating layer having optimal heating characteristics, a PRAM device having high reliability and excellent operating characteristics can be manufactured.Type: GrantFiled: June 23, 2010Date of Patent: October 28, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Seung-Yun Lee, Young Sam Park, Sung Min Yoon, Kyu-Jeong Choi, Nam-Yeal Lee, Byoung-Gon Yu
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Patent number: 8716035Abstract: Provided are a nonvolatile memory cell and a method of manufacturing the same. The nonvolatile memory cell includes a memory transistor and a driver transistor. The memory transistor includes a semiconductor layer, a buffer layer, an organic ferroelectric layer, and a gate electrode, which are disposed on a substrate. The driver transistor includes the semiconductor layer, the buffer layer, a gate insulating layer, and the gate electrode, which are disposed on the substrate. The memory transistor and the driver transistor are disposed on the same substrate. The nonvolatile memory cell is transparent in a visible light region.Type: GrantFiled: September 10, 2013Date of Patent: May 6, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Sung Min Yoon, Chun Won Byun, Shin Hyuk Yang, Sang Hee Park, Soon Won Jung, Seung Youl Kang, Chi Sun Hwang, Byoung Gon Yu
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Patent number: 8710866Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.Type: GrantFiled: October 9, 2013Date of Patent: April 29, 2014Assignees: Electronics and Telecomunications Research Institute, Konkuk University Industrial Cooperation Corp.Inventors: Sang Hee Park, Chi Sun Hwang, Sung Min Yoon, Him Chan Oh, Kee Chan Park, Tao Ren, Hong Kyun Leem, Min Woo Oh, Ji Sun Kim, Jae Eun Pi, Byeong Hoon Kim, Byoung Gon Yu
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Patent number: 8694913Abstract: An apparatus and method for managing the layout of a window is provided. The apparatus includes a display unit that displays the window on a screen; the screen is divided into a plurality of display areas; a pointer-position-checking unit that checks the coordinate position of a pointer moved by a user and determines the one display area corresponding to the position of the checked pointer; and a window-size-adjusting unit that moves the window to the one display area where the pointer is positioned and adjusts the size of the window in proportion to the size of the one display area.Type: GrantFiled: July 20, 2010Date of Patent: April 8, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Kuk Kim, Sung-min Yoon
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Publication number: 20140035621Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.Type: ApplicationFiled: October 9, 2013Publication date: February 6, 2014Applicants: Konkuk University Industrial Cooperation Corp, ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sang Hee PARK, Chi Sun HWANG, Sung MIN Yoon, Him Chan OH, Kee Chan PARK, Tao REN, Hong Kyun LEEM, Min Woo OH, Ji Sun KIM, Jae Eun PI, Byeong Hoon KIM, Byoung Gon YU
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Publication number: 20140035622Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.Type: ApplicationFiled: October 9, 2013Publication date: February 6, 2014Applicants: Konkuk University Industrial Cooperation Corp, ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sang Hee PARK, Chi Sun Hwang, Sung Min Yoon, Him Chan Oh, Kee Chan Park, Tao Ren, Hong Kyun Leem, Min Woo Oh, Ji Sun Kim, Jae Eun Pi, Byeong Hoon Kim, Byoung Gon Yu
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Publication number: 20140011297Abstract: Provided are a nonvolatile memory cell and a method of manufacturing the same. The nonvolatile memory cell includes a memory transistor and a driver transistor. The memory transistor includes a semiconductor layer, a buffer layer, an organic ferroelectric layer, and a gate electrode, which are disposed on a substrate. The driver transistor includes the semiconductor layer, the buffer layer, a gate insulating layer, and the gate electrode, which are disposed on the substrate. The memory transistor and the driver transistor are disposed on the same substrate. The nonvolatile memory cell is transparent in a visible light region.Type: ApplicationFiled: September 10, 2013Publication date: January 9, 2014Applicant: ELECTRONICS AND TELECOMMUNICATION RESEARCH INSTITUTEInventors: Sung Min YOON, Chun Won BYUN, Shin Hyuk YANG, Sang Hee PARK, Soon Won JUNG, Seung Youl KANG, Chi Sun HWANG, Byoung Gon YU
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Patent number: 8570066Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.Type: GrantFiled: January 20, 2012Date of Patent: October 29, 2013Assignee: Electronics and Telecommunications Research InstituteInventors: Sang Hee Park, Chi Sun Hwang, Sung Min Yoon, Him Chan Oh, Kee Chan Park, Tao Ren, Hong Kyun Leem, Min Woo Oh, Ji Sun Kim, Jae Eun Pi, Byeong Hoon Kim, Byoung Gon Yu
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Patent number: 8558295Abstract: Provided are a nonvolatile memory cell and a method of manufacturing the same. The nonvolatile memory cell includes a memory transistor and a driver transistor. The memory transistor includes a semiconductor layer, a buffer layer, an organic ferroelectric layer, and a gate electrode, which are disposed on a substrate. The driver transistor includes the semiconductor layer, the buffer layer, a gate insulating layer, and the gate electrode, which are disposed on the substrate. The memory transistor and the driver transistor are disposed on the same substrate. The nonvolatile memory cell is transparent in a visible light region.Type: GrantFiled: July 19, 2010Date of Patent: October 15, 2013Assignee: Electronics and Telecommunications Research InstituteInventors: Sung Min Yoon, Chun Won Byun, Shin Hyuk Yang, Sang Hee Park, Soon Won Jung, Seung Youl Kang, Chi Sun Hwang, Byoung Gon Yu
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Patent number: RE45356Abstract: Provided are a phase-change memory device using a phase-change material having a low melting point and a high crystallization speed, and a method of fabricating the same. The phase-change memory device includes an antimony (Sb)-selenium (Se) chalcogenide SbxSe100-x phase-change material layer contacting a heat-generating electrode layer exposed through a pore and filling the pore. Due to the use of SbxSe100-x in the phase-change material layer, a higher-speed, lower-power consumption phase-change memory device than a GST memory device can be manufactured.Type: GrantFiled: June 16, 2011Date of Patent: February 3, 2015Assignee: Electronics and Telecommunications Research InstituteInventors: Sung Min Yoon, Nam Yeal Lee, Sang Ouk Ryu, Seung Yun Lee, Young Sam Park, Kyu Jeong Choi, Byoung Gon Yu