Patents by Inventor Sven Albers

Sven Albers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160358897
    Abstract: A method including forming at least one passive structure on a substrate by a build-up process; introducing one or more integrated circuit chips on the substrate; and introducing a molding compound on the at least one passive structure and the one or more integrated circuit chips. A method including forming at least one passive structure on a substrate by a three-dimensional printing process; introducing one or more integrated circuit chips on the substrate; and embedding the at least one passive structure and the one or more integrated circuit chips in a molding compound. An apparatus including a package substrate including at least one three-dimensional printed passive structure and one or more integrated circuit chips embedded in a molding material.
    Type: Application
    Filed: December 9, 2014
    Publication date: December 8, 2016
    Inventors: Sven ALBERS, Andreas WOLTER, Klaus REINGRUBER, Thorsten MEYER
  • Patent number: 9515049
    Abstract: Embodiments of a flexibly-wrapped integrated circuit die device and a method for mounting a flexibly-wrapped integrated circuit die to a substrate are disclosed. In some embodiments, the flexibly-wrapped integrated circuit die device includes a substrate and a flexible integrated circuit die coupled to the substrate in a substantially vertical orientation with reference to a surface of the substrate.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: December 6, 2016
    Assignee: Intel Corporation
    Inventors: Sven Albers, Michael Skinner, Hans-Joachim Barth, Peter Baumgartner, Harald Gossner
  • Publication number: 20160293453
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 14, 2016
    Publication date: October 6, 2016
    Inventors: Sven Albers, Sonja Koller, Thorsten Meyer, Georg Seidemann, Christian Geissler, Andreas Wolter
  • Publication number: 20160247785
    Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: May 4, 2016
    Publication date: August 25, 2016
    Inventors: Michael P. Skinner, Teodora Ossiander, Sven Albers, Georg Seidemann
  • Publication number: 20160240435
    Abstract: An interconnect adaptor may be fabricated having a substantially planar surface, to which a microelectronic package may be electrically attached, and a non-planar surface with at least one interconnect extending from the interconnect adaptor planar surface to the interconnect adaptor non-planar surface. The interconnect adaptor non-planar surface may be shaped to substantially conform to a shape of a microelectronic substrate to which it may be attached, which eliminates the need to bend or otherwise adapt the microelectronic package to conform to the microelectronic substrate.
    Type: Application
    Filed: February 17, 2015
    Publication date: August 18, 2016
    Applicant: INTEL CORPORATION
    Inventors: Christian Geissler, Klaus Reingruber, Sven Albers
  • Publication number: 20160224148
    Abstract: Some forms relate to wearable computing devices that include a “touch pad” like interface. In some forms, the example wearable computing devices may be integrated with (or attached to) textiles (i.e. clothing). In other forms, the example wearable computing devices may be attached directly to the skin of someone (i.e., similar to a bandage) that utilizes any of the example wearable computing devices. The example wearable computing devices include a flexible touch pad that may allow a user of the wearable computing device to more easily operate the wearable computing device. The example wearable computing devices described herein may include a variety of electronics. Some examples include a power supply and/or a communication device among other types of electronics.
    Type: Application
    Filed: December 16, 2014
    Publication date: August 4, 2016
    Inventors: Sven ALBERS, Klaus Reingruber, Teodora Ossiander, Andreas Wolter, Sonja Koller, Georg Seidemann, Jan Proschwitz, Hans-Joachim Barth, Bastiaan Elshof
  • Patent number: 9397019
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: July 19, 2016
    Assignee: Intel IP Corporation
    Inventors: Sven Albers, Sonja Koller, Thorsten Meyer, Georg Seidemann, Christian Geissler, Andreas Wolter
  • Patent number: 9385105
    Abstract: A semiconductor device includes: a chip having at least one electrically conductive contact at a first side of the chip; an extension layer extending laterally from one or more sides of the chip; a redistribution layer on a surface of the extension layer and the first side, and coupled to the contact; an interposer having at least one electrically conductive contact at a first surface of the interposer and coupled to the redistribution layer, and at least one electrically conductive contact at a second surface of the interposer opposite to the first surface; a molding material at least partially enclosing the chip and the redistribution layer, and in contact with the interposer. Another semiconductor device includes: an interposer; a redistribution layer over the interposer; a circuit having first and second circuit portions, wherein the redistribution layer includes the first circuit portion, and the interposer includes the second circuit portion.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: July 5, 2016
    Assignee: Intel Deutschland GmbH
    Inventors: Thorsten Meyer, Gerald Ofner, Bernd Waidhas, Hans-Joachim Barth, Sven Albers, Reinhard Golly, Philipp Riess, Bernd Ebersberger
  • Publication number: 20160190107
    Abstract: An electronic package includes an interposer, a die attached to a first side of the interposer, an embedded electronic package attached to a second side of the interposer, an encapsulation compound, a set of vias providing electrical paths from a first side of the electronic package to the interposer through the encapsulation compound, and a redistribution layer electrically redistributing the set of vias to form a set of interconnect-pads. Either the die or the embedded electronic package, or both, are electrically connected to the interposer.
    Type: Application
    Filed: March 8, 2016
    Publication date: June 30, 2016
    Inventors: Thorsten Meyer, Sven Albers, Andreas Wolter
  • Patent number: 9373588
    Abstract: Embodiments of the present description include stacked microelectronic dice embedded in a microelectronic substrate and methods of fabricating the same. In one embodiment, at least one first microelectronic die is attached to a second microelectronic die, wherein an underfill material is provided between the second microelectronic die and the at least one first microelectronic die. The microelectronic substrate is then formed by laminating the first microelectronic die and the second microelectronic die in a substrate material.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: June 21, 2016
    Assignee: Intel Corporation
    Inventors: Reinhard Mahnkopf, Wolfgang Molzer, Bernd Memmler, Edmund Goetz, Hans-Joachim Barth, Sven Albers, Thorsten Meyer
  • Patent number: 9368461
    Abstract: Disclosed herein are contact pads for use with integrated circuit (IC) packages. In some embodiments, a contact pad disclosed herein may be disposed on a substrate of an IC package, and may include a metal projection portion and a metal recess portion. Each of the metal projection portion and the metal recess portion may have a solder contact surface. The solder contact surface of the metal recess portion may be spaced away from the solder contact surface of the metal projection portion. Related devices and techniques are also disclosed herein, and other embodiments may be claimed.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: June 14, 2016
    Assignee: INTEL CORPORATION
    Inventors: Sven Albers, Georg Seidemann, Sonja Koller, Stephan Stoeckl, Shubhada H. Sahasrabudhe, Sandeep B. Sane
  • Publication number: 20160148920
    Abstract: Embodiments of the present description include stacked microelectronic dice embedded in a microelectronic substrate and methods of fabricating the same. In one embodiment, at least one first microelectronic die is attached to a second microelectronic die, wherein an underfill material is provided between the second microelectronic die and the at least one first microelectronic die. The microelectronic substrate is then formed by laminating the first microelectronic die and the second microelectronic die in a substrate material.
    Type: Application
    Filed: January 28, 2016
    Publication date: May 26, 2016
    Applicant: Intel Corporation
    Inventors: Reinhard Mahnkopf, Wolfgang Molzer, Bernd Memmler, Edmund Goetz, Hans-Joachim Barth, Sven Albers, Thorsten Meyer
  • Patent number: 9343389
    Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: May 17, 2016
    Assignee: Intel Corporation
    Inventors: Michael P. Skinner, Teodora Ossiander, Sven Albers, Georg Seidemann
  • Patent number: 9312198
    Abstract: An electronic package includes an interposer, a die attached to a first side of the interposer, an embedded electronic package attached to a second side of the interposer, an encapsulation compound, a set of vias providing electrical paths from a first side of the electronic package to the interposer through the encapsulation compound, and a redistribution layer electrically redistributing the set of vias to form a set of interconnect-pads. Either the die or the embedded electronic package, or both, are electrically connected to the interposer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 12, 2016
    Assignee: INTEL DEUTSCHLAND GMBH
    Inventors: Thorsten Meyer, Sven Albers, Andreas Wolter
  • Patent number: 9299672
    Abstract: Disclosed herein are contact pads for use with integrated circuit (IC) packages. In some embodiments, a contact pad disclosed herein may be disposed on a substrate of an IC package, and may include a metal projection portion and a metal recess portion. Each of the metal projection portion and the metal recess portion may have a solder contact surface. The solder contact surface of the metal recess portion may be spaced away from the solder contact surface of the metal projection portion. Related devices and techniques are also disclosed herein, and other embodiments may be claimed.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: March 29, 2016
    Assignee: INTEL CORPORATION
    Inventors: Sven Albers, Georg Seidemann, Sonja Koller, Stephan Stoeckl, Shubhada H. Sahasrabudhe, Sandeep B. Sane
  • Publication number: 20150357311
    Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: August 14, 2015
    Publication date: December 10, 2015
    Inventors: Michael P. Skinner, Teodora Ossiander, Sven Albers, Georg Seidemann
  • Patent number: 9209143
    Abstract: An apparatus comprises a first integrated circuit (IC) die that includes a top layer, a bottom surface, a sidewall surface extending from a top surface of the top layer to the bottom surface, and at least one multi-surface contact pad, a second IC die including a top layer, a bottom surface, a sidewall surface extending from a top surface of the top layer to the bottom surface, and at least one multi-surface contact pad, wherein the second IC die is arranged adjacent to the first IC die, and includes an electrically conductive bond in contact with at least one of the top surface or the side surface of the multi-surface contact pad of the first IC die and the top surface of the multi-surface contact pad of the second IC die.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: December 8, 2015
    Assignee: Intel IP Corporation
    Inventors: Georg Seidemann, Sven Albers, Teodora Ossiander, Michael Skinner, Hans-Joachim Barth, Harald Gossner, Reinhard Mahnkopf, Christian Mueller, Wolfgang Molzer
  • Publication number: 20150333022
    Abstract: Disclosed herein are contact pads for use with integrated circuit (IC) packages. In some embodiments, a contact pad disclosed herein may be disposed on a substrate of an IC package, and may include a metal projection portion and a metal recess portion. Each of the metal projection portion and the metal recess portion may have a solder contact surface. The solder contact surface of the metal recess portion may be spaced away from the solder contact surface of the metal projection portion. Related devices and techniques are also disclosed herein, and other embodiments may be claimed.
    Type: Application
    Filed: May 16, 2014
    Publication date: November 19, 2015
    Inventors: Sven Albers, Georg Seidemann, Sonja Koller, Stephan Stoeckl, Shubhada H. Sahasrabudhe, Sandeep B. Sane
  • Publication number: 20150282367
    Abstract: An electronic assembly that includes a first electronic component that includes a first substrate having a front side and a back side and at least one electronic assembly mounted on the front side of the first substrate, a second electronic component that includes a second substrate having a front side and a back side and at least one electronic assembly mounted on the front side of the second substrate, and wherein the back side of the first substrate is directly attached to the back side of the second substrate.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 1, 2015
    Inventors: Hans-Joachim Barth, Reinhard Mahnkopf, Sven Albers, Thorsten Meyer
  • Publication number: 20150282308
    Abstract: Passive electrical devices are described with a polymer carrier. In one example, a conductive layer is formed over a polymer substrate in a pattern to form a passive electrical device and at least two terminals of the device. A plurality of external connection pads are connected to the terminals of the device.
    Type: Application
    Filed: March 28, 2014
    Publication date: October 1, 2015
    Inventors: Thorsten Meyer, Gerald Ofner, Sven Albers, Reinhard Mahnkopf