Abstract: A strong but lightweight garment hanger includes a unitary body that can be made of Aluminum or plastic. A hook support member depends down from the hook of the hanger, and first and second arm members extend down from the hook support member. For strength, each arm member includes an inner arm and an outer arm connected to the inner arm by connector segments. A lower support member extends between the arm members and includes upper and lower elements and a strengthening web between the lower and upper elements.

Abstract: Metabolic auxotroph of Vibrio cholerae 0139 synonym Bengal which has a mutation in its hem A gene and which is not capable of synthesizing aminolevulinic acid (ALA) de novo and which is obtained from a parent strain originally isolated from a patient's coproculture having all the identifying characteristics of Vibrio cholerae 0139 synonym Bengal is described. In this strain the hem A gene is mutated by inserting a kanamycin resistant gene cassette. Another metabolic auxotroph of Vibrio cholerae 01 El Tor where the hem A gene is mutated by a frame shift mutation is disclosed. Methods of producing the strains are disclosed.

Abstract: A method and apparatus for assigning the data rate and/or power level to the mobile terminals without determining the highest theoretical system throughput, and without determining the highest weighted system throughput. An order is imposed on the terminals and the data rate and/or power covariance matrices are assigned such that the data rates of the terminals having a lower index in the order will not be decreased due to the presence of the terminals having a higher index in the order, and this is accomplished without changing the power covariance matrixes of the antennas involved in the communication with the lower index terminals. Thus, the assignment is made to the terminals based on the terminals requirements without regard to the interference introduced by the terminals with a higher index in the order since this interference will be compensated for by the compensation technique when the compensation technique process the terminals in accordance with the order.

Abstract: The present invention relates to novel processes and compositions for protecting drugs, especially water soluble drugs in aqueous environments. More specifically, this process entails coating drugs with a controlled phase composition wax/lipid middle layer for controlling migration of the drug toward the composition's surface during preparation and a polymeric outer layer.

Abstract: A method and apparatus to compensate for interference between signals within a wireless communication system using dirty paper coding to compensate for interference on the downlink and multi-user detection to compensate for interference on uplink.

Abstract: Described here are systems and methods for providing data starting from start codes aligned with byte boundaries in multiple byte words. A start code is written starting at a byte in a middle portion of a data word in a memory. An address associated with the byte is written in a table. Data is fetched from the memory starting from the byte.

Abstract: Presented herein is a compressed structure for writing slice group start codes into a start code table, for use with a video decoding system. One or more start codes are written to a start code table. The presentation time information is written to the start code table.

Abstract: A method and apparatus for assigning the data rate and/or power level to the mobile terminals without determining the highest theoretical system throughput, and without determining the highest weighted system throughput. An order is imposed on the terminals and the data rate and/or power covariance matrices are assigned such that the data rates of the terminals having a lower index in the order will not be decreased due to the presence of the terminals having a higher index in the order, and this is accomplished without changing the power covariance matrixes of the antennas involved in the communication with the lower index terminals. Thus, the assignment is made to the terminals based on the terminals requirements without regard to the interference introduced by the terminals with a higher index in the order since this interference will be compensated for by the compensation technique when the compensation technique process the terminals in accordance with the order.

Abstract: A method and apparatus to compensate for interference between signals within a wireless communication system using dirty paper coding to compensate for interference on the downlink and multi-user detection to compensate for interference on uplink.

Abstract: In a device for feeding articles, cylindrical feed screws having left and right hand pitched helical grooves are arranged in parallel and are driven rotationally in opposite directions such that an article deposited in the space between the roots of the grooves at one corresponding end of the grooves will be advanced axially to the opposite ends for exiting from between the feed screws.

Abstract: An electrically erasable and programmable nonvolatile memory device (EEPROM) such as a flash memory, is pin compatible with a dynamic random access memory device (DRAM), such that flash memory may be connected to a DRAM bus. Preferably, the flash memory is read and write timing-compatible with the DRAM read and write signals and is also preferably block read and block write timing compatible with DRAM block read and block write signals. The flash memory accepts signals to perform sleep and erase functions from signal lines of a DRAM bus which are not used by a DRAM. In order to perform a block erase, which is a characteristic of flash memory, the device preferably accepts an instruction to perform a block erase from signal lines of a DRAM bus which are not used by a DRAM and a block address for the block erase from the most significant bit address lines of the DRAM bus.

Abstract: Nonvolatile integrated circuit memory devices, such as EEPROMs, use unselected shared latching sense amplifiers to latch data from memory cells which are to be reprogrammed after a page erase, and to resupply the latch data to the memory cells which are to be programmed after erase, to thereby internally reprogram the latched data into erased memory cells after page programming. Transferring circuits and methods are provided for transferring data between shared latching sense amplifiers to permit internal reprogramming. High speed and simplified reprogramming of EEPROMs is thereby provided.

Abstract: An array of floating gate transistors is arranged so that in the transistors within the even numbered rows, the bit line on the left side of the transistor serves as the drain, and the bit line on the right side of the transistor serves as the source, and the floating gate extends over the left side of the transistor channel. Conversely, in the odd numbered rows, the bit line on the right side of each transistor serves as the drain, the bit line on the left side of each transistor serves as the source, and the floating gate extends over the left side of the transistor channel. Thus, in order for the bit line decoder to determine which bit line is to be grounded and which bit line is to be connected to a sense amplifier, the bit line decoder also receives signals indicative of the row which has been addressed. In one embodiment, the array comprises redundant rows. The decoder is constructed so that any redundant rows can be used to replace either an odd or even-numbered row in the array.

Abstract: An EEPROM constructed in accordance with our invention includes a voltage multiplier for generating an erase voltage and a voltage regulator circuit for controlling the magnitude of the erase voltage. The voltage regulator circuit includes a capacitive voltage divider for providing a first voltage proportional to the erase voltage, a reference voltage lead for providing a reference voltage and a control circuit for controlling the voltage multipler circuit so that if the first voltage is less than the reference voltage, the voltage multiplier circuit will increase the erase voltage, but if the first voltage is greater than the reference voltage, the voltage multiplier will not continue to increase the erase voltage. The voltage multiplier includes novel capacitors and transistors constructed using standard EEPROM processing to withstand high voltages without breaking down.

Abstract: An EEPROM constructed in accordance with our invention includes a voltage multiplier for generating an erase voltage and a voltage regulator circuit for controlling the magnitude of the erase voltage. The voltage regulator circuit includes means for providing a first voltage proportional to the erase voltage, means for providing a reference voltage on a reference voltage lead, and means for controlling the voltage multiplier circuit so that if the first voltage is less than the reference voltage, the voltage multiplier circuit will increase the erase voltage, but if the first voltage is greater than the reference voltage, the voltage multiplier will not continue to increase the erase voltage. The voltage multiplier includes novel capacitors and transistors constructed using standard EEPROM processing to withstand high voltages without breaking down.

Abstract: An EEPROM receives a first address from a microprocessor. If the first address equals a first predetermined value, the EEPROM goes into a programming mode. If the first address equals a second predetermined value, the EEPROM goes into an erase mode. The EEPROM interprets a second address received from the microprocessor as indicating the location where data is to be stored in the EEPROM. The EEPROM generates an internal write pulse which remains active until the EEPROM receives a subsequent write instruction from the microprocessor. In this way, it is not necessary to generate a wait instruction to the microprocessor to halt the microprocessor while the EEPROM is storing data. Also, it is not necessary to provide additional circuitry to control whether the EEPROM goes into the erase or programming modes.