Patents by Inventor Syed M. Alam

Syed M. Alam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200235288
    Abstract: The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.
    Type: Application
    Filed: January 16, 2020
    Publication date: July 23, 2020
    Applicant: Everspin Technologies, Inc.
    Inventors: Sumio IKEGAWA, Han Kyu LEE, Sanjeev AGGARWAL, Jijun SUN, Syed M. ALAM, Thomas ANDRE
  • Publication number: 20200235289
    Abstract: The present disclosure is drawn to, among other things, a magnetoresistive memory. The magnetoresistive memory comprises a plurality of magnetoresistive memory devices, wherein each magnetoresistive memory device includes a fixed magnetic region, a free magnetic region, and an intermediate region disposed in between the fixed and free magnetic regions. The magnetoresistive memory further comprises a first conductor extending adjacent each magnetoresistive memory device of the plurality of magnetoresistive devices, wherein the first conductor is in electrical contact with the free magnetic region of each magnetoresistive memory device.
    Type: Application
    Filed: January 18, 2019
    Publication date: July 23, 2020
    Applicant: Everspin Technologies, Inc.
    Inventors: Syed M. ALAM, Thomas ANDRE, Frederick MANCOFF, Sumio IKEGAWA
  • Patent number: 10657065
    Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: May 19, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas S. Andre, Syed M. Alam, Chitra K. Subramanian, Javed S. Barkatullah
  • Patent number: 10658013
    Abstract: The present disclosure is drawn to, among other things, a magnetic memory. The magnetic memory comprises a first common line, a second common line, and a memory cell. The magnetic memory further includes a bias voltage generation circuit and a voltage driver. The bias voltage generation circuit and the voltage driver are configured to provide driving voltages to the memory cell during access operations.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: May 19, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Syed M. Alam, Frederick Neumeyer
  • Patent number: 10650899
    Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed. Calibration and testing sequences are also supported in which a non-destructive mode preserves data stored in a non-volatile memory array and status bits used to indicate open pages are cleared so later inadvertent delayed write-back operations as a result of the calibration or testing do not corrupt the non-volatile data.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: May 12, 2020
    Assignee: Everspin Technologies, Inc.
    Inventor: Syed M. Alam
  • Patent number: 10614907
    Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: April 7, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Jon Slaughter, Dimitri Houssameddine, Syed M. Alam
  • Patent number: 10608671
    Abstract: A memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page, such that a first level of error correction is performed by the memory device on each of the ECC words associated with a page, and a second level of error correction is performed on the data output by each of the input/output pads, during a particular period of time. Each of the one or more input/output pads of the memory device is configured to provide only one bit of data per ECC word to an external source during an access from the external source.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: March 31, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Thomas Andre
  • Patent number: 10573365
    Abstract: In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to reduce power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving a global word line to a first voltage. Driving the global word line to a first voltage results in a second voltage passed to the word lines. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: February 25, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Syed M. Alam
  • Patent number: 10505538
    Abstract: A switching circuit includes a semiconductor switch having a Gate terminal, and includes first, second, third, and fourth Gate resistors. The Gate resistors have upstream and downstream ends relative to a location of the semiconductor switch or a driven load. The downstream ends connect to the Gate terminal. First, second, third, and fourth buffer switches have Gate terminals and Source terminals, with the Source terminals connected to the upstream ends of the first, second, third, and fourth Gate resistors, respectively. An optional Gate driver integrated circuit (IC) connects to the Gate terminals of the buffer switches. A microcontroller, responsive to circuit measurements, selects switching control values and Gate resistor identities based on the measurements, and transmits switching control signals and a Gate resistor selection signal to select on/off states of the buffer switches and an optimum switching speed for the semiconductor switch.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: December 10, 2019
    Assignee: GM Global Technology Operations LLC
    Inventors: Mohammed K Alam, Mohammad N. Anwar, Syed M. Kadry, Korobi Basher, Goro Tamai, William R. Cawthorne, Subramanian Vadula
  • Publication number: 20190355398
    Abstract: In some examples, a memory device may have at least a first and a second memory array. In some cases, a portion of the bit cells of the first memory array may be coupled to first PMOS-follower circuitry and to second PMOS-follower circuitry. A portions of the bit cells of the second memory array may also be coupled to the second PMOS-follower circuitry and to third PMOS-follower circuitry. Additionally, in some cases, the portion of bit cells of both the first memory array and the second memory array may be coupled to shared preamplifier circuitry.
    Type: Application
    Filed: July 22, 2019
    Publication date: November 21, 2019
    Applicant: Everspin Technologies, Inc.
    Inventors: Syed M. ALAM, Thomas S. ANDRE
  • Patent number: 10475497
    Abstract: Precharging circuits and techniques are presented for use with magnetic memory devices in order to speed up access to the memory cells for reading and writing. Including precharging in the sense amplifiers used to access the memory cells enables self-referenced read operations to be completed more quickly than is possible without precharging. Similarly, precharging can also be used in conjunction with write-back operations in order to allow the data state stored by magnetic tunnel junctions included in the memory cells to be changed more rapidly.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: November 12, 2019
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Chitra Subramanian
  • Patent number: 10446213
    Abstract: The present disclosure is drawn to, among other things, a magnetoresistive memory. The magnetoresistive memory includes a first memory cell, a first access circuit, a second access circuit, and a current generating circuit. The first memory cell includes a first magnetic tunnel junction and a second magnetic tunnel junction. The first access circuit is configured to receive access command signals for accessing the first magnetic tunnel junction. The first access circuit includes a first access switch and a second access switch. The second access circuit is configured to receive access command signals for accessing the second magnetic tunnel junction. The second access circuit includes a third access switch and a fourth access switch. The current generating circuit is configured to generate a first write current through the first magnetic tunnel junction and generate a second write current through the second magnetic tunnel junction based on data input signals.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: October 15, 2019
    Assignee: Everspin Technologies, Inc.
    Inventors: Yaojun Zhang, Syed M. Alam, Thomas Andre
  • Patent number: 10395699
    Abstract: In some examples, a memory device may have at least a first and a second memory array. In some cases, a portion of the bit cells of the first memory array may be coupled to first PMOS-follower circuitry and to second PMOS-follower circuitry. A portion of the bit cells of the second memory array may also be coupled to the second PMOS-follower circuitry and to third PMOS-follower circuitry. Additionally, in some cases, the portions of bit cells of both the first memory array and the second memory array may be coupled to shared preamplifier circuitry.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: August 27, 2019
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Thomas Andre
  • Publication number: 20190221242
    Abstract: The present disclosure is drawn to, among other things, a magnetic memory. The magnetic memory comprises a first common line, a second common line, and a memory cell. The magnetic memory further includes a bias voltage generation circuit and a voltage driver. The bias voltage generation circuit and the voltage driver are configured to provide driving voltages to the memory cell during access operations.
    Type: Application
    Filed: January 18, 2019
    Publication date: July 18, 2019
    Applicant: Everspin Technologies, Inc.
    Inventors: Thomas ANDRE, Syed M. ALAM, Frederick NEUMEYER
  • Publication number: 20190221247
    Abstract: In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to reduce power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving a global word line to a first voltage. Driving the global word line to a first voltage results in a second voltage passed to the word lines. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell.
    Type: Application
    Filed: January 18, 2019
    Publication date: July 18, 2019
    Applicant: Everspin Technologies, Inc.
    Inventors: Thomas ANDRE, Syed M. ALAM
  • Publication number: 20190213136
    Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.
    Type: Application
    Filed: March 20, 2019
    Publication date: July 11, 2019
    Applicant: Everspin Technologies, Inc.
    Inventors: Thomas S. ANDRE, Syed M. ALAM, Chitra K. SUBRAMANIAN, Javed S. BARKATULLAH
  • Publication number: 20190214070
    Abstract: Techniques and circuits for testing and configuring bias voltage or bias current for write operations in memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation.
    Type: Application
    Filed: March 19, 2019
    Publication date: July 11, 2019
    Applicant: Everspin Technologies, Inc.
    Inventors: Jason JANESKY, Syed M. ALAM, Dimitri HOUSSAMEDDINE, Mark DEHERREA
  • Publication number: 20190199375
    Abstract: In some examples, a memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page, such that a first level of error correction may be performed by the memory device on each of the ECC words associated with a page and a second level of error correction may be performed on the data output by each of the input/output pads during a particular period of time. Each of the one or more input/output pads of the memory device may be configured to provide only one bit of data per ECC word to an external source during an access from an external source.
    Type: Application
    Filed: February 28, 2019
    Publication date: June 27, 2019
    Applicant: Everspin Technologies, Inc.
    Inventors: Syed M. ALAM, Thomas ANDRE
  • Patent number: 10304511
    Abstract: The present disclosure is drawn to, among other things, a magnetoresistive memory. The magnetoresistive memory comprises a first memory cell, a first clock-generating circuit, and a second clock-generating circuit. The first clock-generating circuit is configured to provide a first output signal and a second output signal. The second clock-generating circuit is configured to provide a third output signal and a fourth output signal. The first output signal, the second output signal, the third output signal, and the fourth output signal are configured for controlling access operations for the first memory cell.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: May 28, 2019
    Assignee: Everspin Technologies Inc.
    Inventors: Syed M. Alam, Yaojun Zhang, Thomas Andre
  • Publication number: 20190156878
    Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.
    Type: Application
    Filed: December 12, 2018
    Publication date: May 23, 2019
    Applicant: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Thomas ANDRE, Dimitri HOUSSAMEDDINE, Syed M. ALAM, Jon SLAUGHTER, Chitra SUBRAMANIAN