Patents by Inventor Syed M. Alam

Syed M. Alam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12299182
    Abstract: The present disclosure is drawn to, among other things, a storage device. The storage device may include a magnetic tunnel junction (MTJ)-based storage array and a communication interface. The MTJ-based storage array may be configured to be damaged by a shorting voltage based on detection of a tamper event.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: May 13, 2025
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Sanjeev Aggarwal
  • Publication number: 20250113741
    Abstract: A magnetoresistive random-access memory (MRAM) device includes a magnetoresistive tunnel junction (MTJ) device, an electrode, and a coupling layer. The MTJ device includes a free layer, a fixed layer, and a tunnel barrier layer positioned between the free layer and the fixed layer. The coupling layer is positioned between and coupling the electrode and the MTJ device. The coupling layer includes spin Hall channel (SHC) material. The free layer, the fixed layer, and the tunnel barrier layer are stacked in a first direction to form MTJ device. The electrode is nonaligned with the MTJ device such that the electrode is spaced away from the MTJ in a second direction that is different from the first direction.
    Type: Application
    Filed: September 26, 2024
    Publication date: April 3, 2025
    Applicant: Everspin Technologies, Inc.
    Inventors: Sumio IKEGAWA, Kerry Joseph NAGEL, Raj KUMAR, Syed M. ALAM
  • Publication number: 20250068341
    Abstract: Systems and techniques include identifying a network layer for performing a memory operation, identifying a subset of a plurality of configuration bit clusters of a non-volatile distributed memory that are mapped to the identified network layer using a cluster mapping, in response to identifying the subset of the plurality of configuration bit clusters, activating the subset of the plurality of configuration bit clusters, loading network component data from the subset of the plurality of configuration bit clusters into a local buffer, and applying the network component data to the network layer for performing the memory operation.
    Type: Application
    Filed: February 28, 2024
    Publication date: February 27, 2025
    Applicant: Everspin Technologies, Inc.
    Inventors: Syed M. ALAM, Michael SADD, Jacob T. WILLIAMS
  • Publication number: 20250061933
    Abstract: The present disclosure is drawn to a magnetoresistive device including an array of memory cells arranged in rows and columns, each memory cell comprising a magnetic tunnel junction, each row comprising a word line, and each column comprising a bit line; a column select device that selects a bit line. The magnetoresistive device also includes a sense amplifier comprising a first input corresponding to a selected bit line, a second input corresponding to a reference bit line, and a data output. The plurality of columns comprise a reference column, the reference column comprising a conductive element coupled to the magnetic tunnel junctions in the reference column.
    Type: Application
    Filed: November 1, 2024
    Publication date: February 20, 2025
    Applicant: Everspin Technologies, Inc.
    Inventors: Syed M. ALAM, Yaojun ZHANG, Frederick NEUMEYER
  • Publication number: 20250029645
    Abstract: The present disclosure is drawn to, among other things, an antifuse circuit. The antifuse circuit includes a plurality of antifuse bitcells and a reference resistor. Each antifuse bitcell includes two or more memory bits and a reference resistor. The two or more memory bits are configured to be in a programmed state and at least one unprogrammed state.
    Type: Application
    Filed: October 8, 2024
    Publication date: January 23, 2025
    Applicant: Everspin Technologies, Inc.
    Inventor: Syed M. ALAM
  • Publication number: 20240419361
    Abstract: The present disclosure is drawn to, among other things, a method for programming a memory device comprising a plurality of memory arrays. The method may include receiving a command to program one or more of the plurality of memory arrays and programming the one or more of the plurality of memory arrays based on the command. The method may optionally include erasing the one or more of the plurality of memory arrays prior to the programming.
    Type: Application
    Filed: August 22, 2024
    Publication date: December 19, 2024
    Applicant: Everspin Technologies, Inc.
    Inventors: Syed M. ALAM, Iftekhar RAHMAN, Pedro SANCHEZ
  • Publication number: 20240420796
    Abstract: A memory device including a first configuration bit group including a plurality of bits, the plurality of bits including: a plurality of configuration bits; at least one redundant configuration bit; a plurality of configuration bit multiplexers each configured to receive (i) a first input from a first bit in the plurality of bits and/or a second input from a second bit in the plurality of bits and (ii) a third input from a decoder, each of the first, second, and third inputs indicating a respective logical state, wherein the logical state includes a first state or a second state; and wherein, based on the logical state of the third input received from the decoder, each configuration bit multiplexer is configured to output: the logical state of the first input from the first bit, or the logical state of the second input from the second bit.
    Type: Application
    Filed: June 11, 2024
    Publication date: December 19, 2024
    Applicant: Everspin Technologies, Inc.
    Inventors: Syed M. ALAM, Jacob T. WILLIAMS, Michael A. SADD, Kerry Joseph NAGEL, Sumio IKEGAWA, Frederick B. MANCOFF, Sanjeev AGGARWAL
  • Patent number: 12167702
    Abstract: The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.
    Type: Grant
    Filed: March 20, 2023
    Date of Patent: December 10, 2024
    Assignee: Everspin Technologies, Inc.
    Inventors: Sumio Ikegawa, Han Kyu Lee, Sanjeev Aggarwal, Jijun Sun, Syed M. Alam, Thomas Andre
  • Patent number: 12165684
    Abstract: The present disclosure is drawn to a magnetoresistive device including an array of memory cells arranged in rows and columns, each memory cell comprising a magnetic tunnel junction, each row comprising a word line, and each column comprising a bit line; a column select device that selects a bit line. The magnetoresistive device also includes a sense amplifier comprising a first input corresponding to a selected bit line, a second input corresponding to a reference bit line, and a data output. The plurality of columns comprise a reference column, the reference column comprising a conductive element coupled to the magnetic tunnel junctions in the reference column.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: December 10, 2024
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Yaojun Zhang, Frederick Neumeyer
  • Patent number: 12142309
    Abstract: The present disclosure is drawn to, among other things, an antifuse circuit. The antifuse circuit includes a plurality of antifuse bitcells and a reference resistor. Each antifuse bitcell includes two or more memory bits and a reference resistor. The two or more memory bits are configured to be in a programmed state and at least one unprogrammed state.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: November 12, 2024
    Assignee: Everspin Technologies, Inc.
    Inventor: Syed M. Alam
  • Publication number: 20240361906
    Abstract: The present disclosure is drawn to, among other things, a method of managing a magnetoresistive memory (MRAM) device. In some aspects, the method includes receiving a configuration bit from a write mode configuration register. In response to determining the configuration bit is a first value, the MRAM device is operated in a NOR emulation mode. In response to determining the configuration bit is a second value, the MRAM device is operated in a persistent memory mode.
    Type: Application
    Filed: July 5, 2024
    Publication date: October 31, 2024
    Applicant: Everspin Technologies, Inc.
    Inventors: Syed M. ALAM, Cristian P. MASGRAS
  • Patent number: 12112067
    Abstract: The present disclosure is drawn to, among other things, a method for programming a memory device comprising a plurality of memory arrays. The method may include receiving a command to program one or more of the plurality of memory arrays and programming the one or more of the plurality of memory arrays based on the command. The method may optionally include erasing the one or more of the plurality of memory arrays prior to the programming.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: October 8, 2024
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Iftekhar Rahman, Pedro Sanchez
  • Publication number: 20240304228
    Abstract: 1. The present disclosure is drawn to, among other things, a method for accessing memory using dual standby modes, the method including receiving a first standby mode indication selecting a first standby mode from a first standby mode or a second standby mode, configuring a read bias system to provide a read bias voltage and a write bias system to provide approximately no voltage, or any voltage outside the necessary range for write operation, based on the first standby mode, receiving a second standby mode indication selecting the second standby mode, and configuring the read bias system to provide at least the read bias voltage and the write bias system to provide a write bias voltage based on the second standby mode, the read bias voltage being lower than the write bias voltage.
    Type: Application
    Filed: May 20, 2024
    Publication date: September 12, 2024
    Applicant: Everspin Technologies, Inc.
    Inventor: Syed M. ALAM
  • Patent number: 12067232
    Abstract: The present disclosure is drawn to, among other things, a method of managing a magnetoresistive memory (MRAM) device. In some aspects, the method includes receiving a configuration bit from a write mode configuration register. In response to determining the configuration bit is a first value, the MRAM device is operated in a NOR emulation mode. In response to determining the configuration bit is a second value, the MRAM device is operated in a persistent memory mode.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: August 20, 2024
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Cristian P. Masgras
  • Patent number: 12020769
    Abstract: The present disclosure is drawn to, among other things, a method for accessing memory using dual standby modes, the method including receiving a first standby mode indication selecting a first standby mode from a first standby mode or a second standby mode, configuring a read bias system to provide a read bias voltage and a write bias system to provide approximately no voltage, or any voltage outside the necessary range for write operation, based on the first standby mode, receiving a second standby mode indication selecting the second standby mode, and configuring the read bias system to provide at least the read bias voltage and the write bias system to provide a write bias voltage based on the second standby mode, the read bias voltage being lower than the write bias voltage.
    Type: Grant
    Filed: March 24, 2023
    Date of Patent: June 25, 2024
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventor: Syed M. Alam
  • Patent number: 12020770
    Abstract: 1. The present disclosure is drawn to, among other things, a method for accessing memory using dual standby modes, the method including receiving a first standby mode indication selecting a first standby mode from a first standby mode or a second standby mode, configuring a read bias system to provide a read bias voltage and a write bias system to provide approximately no voltage, or any voltage outside the necessary range for write operation, based on the first standby mode, receiving a second standby mode indication selecting the second standby mode, and configuring the read bias system to provide at least the read bias voltage and the write bias system to provide a write bias voltage based on the second standby mode, the read bias voltage being lower than the write bias voltage.
    Type: Grant
    Filed: March 24, 2023
    Date of Patent: June 25, 2024
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventor: Syed M. Alam
  • Publication number: 20240112713
    Abstract: A scan chain circuitry for a memory device includes a first non-volatile storage bit (nvbit) configured to receive a shared control signal, a second nvbit configured to receive the shared control signal, a first flip-flop connected to the first nvbit, and a second flip-flop connected to the second nvbit and the first flip-flop. The first flip-flop enables loading a first data in (din) to the first nvbit based on a clock signal, and the second flip-flop enables loading a second din to the second nvbit based on the clock signal.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 4, 2024
    Applicant: Everspin Technologies, Inc.
    Inventors: Syed M. ALAM, Jacob T. WILLIAMS
  • Publication number: 20240006011
    Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.
    Type: Application
    Filed: September 15, 2023
    Publication date: January 4, 2024
    Applicant: Everspin Technologies, Inc.
    Inventors: Syed M. ALAM, Jason JANESKY, Han Kyu LEE, Hamid ALMASI, Pedro SANCHEZ, Cristian P. MASGRAS, Iftekhar RAHMAN, Sumio IKEGAWA, Sanjeev AGGARWAL, Dimitri HOUSSAMEDDINE, Frederick Charles NEUMEYER
  • Publication number: 20230403011
    Abstract: A memory device includes a printed circuit board, a magnetoresistive random-access memory (MRAM) device coupled to the printed circuit board, a controller or control circuitry, wherein the controller or control circuitry is integrated into, embedded in, or otherwise incorporated into the MRAM device, and a field programmable gate array (FPGA) coupled to the printed circuit board and in communication with the controller or control circuitry.
    Type: Application
    Filed: June 6, 2023
    Publication date: December 14, 2023
    Applicant: Everspin Technologies, Inc.
    Inventors: Syed M. ALAM, Sanjeev AGGARWAL
  • Publication number: 20230384930
    Abstract: The present disclosure is drawn to, among other things, a method of managing a magnetoresistive memory (MRAM) device. In some aspects, the method includes receiving a configuration bit from a write mode configuration register. In response to determining the configuration bit is a first value, the MRAM device is operated in a NOR emulation mode. In response to determining the configuration bit is a second value, the MRAM device is operated in a persistent memory mode.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Applicant: Everspin Technologies, Inc.
    Inventors: Syed M. ALAM, Cristian P. MASGRAS