Patents by Inventor Syed M. Alam

Syed M. Alam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • WORD LINE AUTO-BOOTING IN A SPIN-TORQUE MAGNETIC MEMORY HAVING LOCAL SOURCE LINES
    Publication number: 20170178709
    Abstract: In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to reduce power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving the word line to a first word line voltage. After such driving, the word line isolated. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell. Additional embodiments include the use of a supplemental voltage provider that is able to further boost or hold the isolated word line at the needed voltage level.
    Type: Application
    Filed: March 8, 2017
    Publication date: June 22, 2017
    Inventors: Thomas Andre, Syed M. Alam
  • Write verify programming of a memory device
    Patent number: 9679627
    Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: June 13, 2017
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Dimitri Houssameddine, Syed M. Alam, Jon Slaughter, Chitra Subramanian
  • MEMORY DEVICE WITH SHARED READ/WRITE CIRCUITRY
    Publication number: 20170125079
    Abstract: In some examples, a memory device may be configured to use shared read circuitry to sample a voltage drop across both a bit cell and a resistive circuit in order to perform a comparison that produces an output corresponding to the bit stored in the bit cell. The shared read circuitry can include a shared sense amplifier as well as shared N-MOS and P-MOS followers used to apply read voltages across the bit cell and resistive circuit.
    Type: Application
    Filed: December 1, 2016
    Publication date: May 4, 2017
    Inventors: Syed M. Alam, Chitra K. Subramanian
  • BIAS CONFIGURATION FOR WRITE OPERATIONS IN MEMORY
    Publication number: 20170117029
    Abstract: Techniques and circuits for testing and configuring bias voltage or bias current for write operations in memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation.
    Type: Application
    Filed: January 9, 2017
    Publication date: April 27, 2017
    Inventors: Jason Janesky, Syed M. Alam, Dimitri Houssameddine, Mark Deherrera
  • ECC WORD CONFIGURATION FOR SYSTEM-LEVEL ECC COMPATIBILITY
    Publication number: 20170104498
    Abstract: In some examples, a memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page, such that a first level of error correction may be performed by the memory device on each of the ECC words associated with a page and a second level of error correction may be performed on the data output by each of the input/output pads during a particular period of time. Each of the one or more input/output pads of the memory device may be configured to provide only one bit of data per ECC word to an external source during an access from an external source.
    Type: Application
    Filed: December 20, 2016
    Publication date: April 13, 2017
    Inventors: Syed M. Alam, Thomas Andre
  • CIRCUIT AND METHOD FOR CONTROLLING MRAM CELL BIAS VOLTAGES
    Publication number: 20170092347
    Abstract: A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array.
    Type: Application
    Filed: December 5, 2016
    Publication date: March 30, 2017
    Inventors: Dietmar Gogl, Syed M. Alam, Thomas Andre
  • MEMORY DEVICE WITH TIMING OVERLAP MODE
    Publication number: 20170084324
    Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.
    Type: Application
    Filed: December 6, 2016
    Publication date: March 23, 2017
    Inventors: Thomas Andre, Syed M. Alam, Halbert S. Lin
  • Word line auto-booting in a spin-torque magnetic memory having local source lines
    Patent number: 9601175
    Abstract: In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to conserve power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving the word line to a first word line voltage. After such driving, the word line isolated. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell. Additional embodiments include the use of a supplemental voltage provider that is able to further boost or hold the isolated word line at the needed voltage level.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: March 21, 2017
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Syed M. Alam
  • SHORT DETECTION AND INVERSION
    Publication number: 20170069397
    Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.
    Type: Application
    Filed: November 18, 2016
    Publication date: March 9, 2017
    Inventors: Thomas Andre, Jon Slaughter, Dimitri Houssameddine, Syed M. Alam
  • MEMORY DEVICE WITH PAGE EMULATION MODE
    Publication number: 20170060691
    Abstract: In some examples, a memory is configured to write multiple pages of an internal page size from a cache on the memory to a memory array on the memory in response to receiving a single precharge command when in a page emulation mode. When in the page emulation mode, the memory also reads multiple pages of the internal page size from the memory array and stores them in the cache in response to receiving a single activate command.
    Type: Application
    Filed: November 9, 2016
    Publication date: March 2, 2017
    Inventors: Syed M. Alam, Thomas Andre
  • Boosted supply voltage generator and method therefore
    Patent number: 9583169
    Abstract: A boosted supply voltage generator is selectively activated and deactivated to allow operations that are sensitive to variations on the boosted voltage to be performed with a stable boosted voltage. Techniques for deactivating and reactivating the voltage generator are also disclosed that enable more rapid recovery from deactivation such that subsequent operations can be commenced sooner. Such techniques include storing state information corresponding to the voltage generator when deactivated, where the stored state information is used when reactivating the voltage generator. Stored state information can include a state of a clock signal provided to the voltage generator.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: February 28, 2017
    Assignee: Everspin Technologies, Inc.
    Inventors: Dietmar Gogl, Syed M. Alam, Thomas Andre, Halbert S. Lin
  • Memory device with reduced test time
    Patent number: 9575125
    Abstract: In some examples, a memory device generates and exposes parity/difference information to a test system to reduce overall test time. The parity/difference information may be generated based on parity bits read from the memory device and parity bits produced from data bits stored in the memory device. In some cases, the parity/difference information may be compared to an expected parity/difference to determine a number of correctable errors which occurred during testing, while the data bits may be compared to expected data to determine a number of uncorrectable errors which occurred during testing.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: February 21, 2017
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Syed M. Alam, William Meadows
  • Tamper detection and response in a memory device
    Patent number: 9569640
    Abstract: A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements. When a tamper detection check is performed, a comparison between the reference bits and the current state of the detection memory cells is used to determine whether any of the detection memory cells have changed state from their initial predetermined states. Based on the comparison, a tamper detect indication is flagged if a threshold level of change is determined.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: February 14, 2017
    Assignee: Everspin Technologies, Inc.
    Inventors: Chitra K. Subramanian, Halbert S. Lin, Syed M. Alam, Thomas Andre
  • Memory device with timing overlap mode and precharge timing circuit
    Patent number: 9552849
    Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: January 24, 2017
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Syed M. Alam, Halbert S Lin
  • Circuit and method for controlling MRAM cell bias voltages
    Patent number: 9542989
    Abstract: A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: January 10, 2017
    Assignee: Everspin Technologies, Inc.
    Inventors: Dietmar Gogl, Syed M. Alam, Thomas Andre
  • Configuration and testing for magnetoresistive memory to ensure long term continuous operation
    Patent number: 9543041
    Abstract: Techniques and circuits for testing and configuring magnetic memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation. Examples include adjustment of bias voltages, sense amplifier offset values, and timing parameters to improve the efficiency of testing operations as well as improve reliability and speed of normal operation.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: January 10, 2017
    Assignee: Everspin Technologies, Inc.
    Inventors: Jason Janesky, Syed M. Alam, Dimitri Houssameddine, Mark Deherrera
  • ECC word configuration for system-level ECC compatibility
    Patent number: 9529672
    Abstract: A memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page, such that a first level of error correction may be performed by the memory device on each of the ECC words associated with a page and a second level of error correction is performed on the data output by each of the input/output pads during a particular period of time.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: December 27, 2016
    Assignee: Everspin Technologies Inc.
    Inventors: Syed M. Alam, Thomas Andre
  • Memory device with page emulation mode
    Patent number: 9529726
    Abstract: In some examples, a memory device is configured to load multiple pages of an internal page size into a cache in response to receiving an activate command and to write multiple pages of the internal page size into a memory array in response to receiving a precharge command. In some implementations, the memory array is arranged to store multiple pages of the internal page size in a single physical row.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: December 27, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Thomas Andre
  • Memory device with shared read/write circuitry
    Patent number: 9530476
    Abstract: In some examples, a memory device may be configured to read or write multiple bit cells as part of the same operation. In some cases, the tunnel junctions forming the bit cells may be arranged to utilize shared read/write circuitry. For instance, the tunnel junctions may be arranged such that both tunnel junctions may be written using the same write voltages. In some cases, the bit cells may be configured such that each bit cell is driven to the same state, while in other cases, select bit cells may be driven high, while others are driven low.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: December 27, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Chitra K. Subramanian
  • MEMORY CONTROLLER AND METHOD FOR INTERLEAVING DRAM AND MRAM ACCESSES
    Publication number: 20160350031
    Abstract: A memory system and memory controller for interleaving volatile and non-volatile memory accesses are described. In the memory system, the memory controller is coupled to the volatile and non-volatile memories using a shared address bus. Activate latencies for the volatile and non-volatile memories are different, and registers are included on the memory controller for storing latency values. Additional registers on the memory controller store precharge latencies for the memories as well as page size for the non-volatile memory. A memory access sequencer on the memory controller asserts appropriate chip select signals to the memories to initiate operations therein.
    Type: Application
    Filed: July 17, 2016
    Publication date: December 1, 2016
    Inventors: Syed M. Alam, Thomas Andre, Dietmar Gogl