Abstract: A spin-torque magnetoresistive memory includes array read circuits and array write circuits coupled to an array of magnetic bits. The array read circuits sample magnetic bits in the array, apply a write current pulse to the magnetic bits to set them to a first logic state, resample the magnetic bits using an additional offset current, and compare the results of sampling and resampling to determine the bit state for each magnetic bit. For each of the magnetic bits in the page having the second logic state, the array write circuits initiate a write-back, wherein the write-back includes applying a second write current pulse having opposite polarity in comparison with the first write current pulse to set the magnetic bit to the second state. A read or write operation may be received after initiation of the write-back where the write-back can be aborted for a portion of the bits in the case of a write operation.

Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.

Abstract: Self-referenced reading of a memory cell in a memory includes first applying a read voltage across the memory cell to produce a sample voltage. After applying the read voltage, a write current is applied to the memory cell to write a first state to the memory cell. After applying the write current, the read voltage is reapplied across the memory cell. An offset current is also applied while the read voltage is reapplied, and the resulting evaluation voltage from reapplying the read voltage with the offset current is compared with the sample voltage to determine the state of the memory cell.

Abstract: A method includes destructively reading bits of a spin torque magnetic random access memory, using error correcting code (ECC) for error correction, and storing inverted or non-inverted data in data-store latches. When a subsequent write operation changes the state of data-store latches, parity calculation and majority detection of the bits are initiated. A majority bit detection and potential inversion of write data minimizes the number of write current pulses. A subsequent write operation received within a specified time or before an original write operation is commenced will cause the majority detection operation to abort.

Abstract: A method of applying a write current to a magnetic tunnel junction device minimizes sub-threshold leakage. NMOS- and PMOS-follower circuits are used in applying the write current, and bias signals for the follower circuits are isolated from global bias signals before the write current is applied.

Abstract: A spin-torque magnetoresistive memory includes array read circuits and array write circuits coupled to an array of magnetic bits. The array read circuits sample magnetic bits in the array, apply a write current pulse to the magnetic bits to set them to a first logic state, resample the magnetic bits using an additional offset current, and compare the results of sampling and resampling to determine the bit state for each magnetic bit. For each of the magnetic bits in the page having the second logic state, the array write circuits initiate a write-back, wherein the write-back includes applying a second write current pulse having opposite polarity in comparison with the first write current pulse to set the magnetic bit to the second state. A read or write operation may be received after initiation of the write-back where the write-back can be aborted for a portion of the bits in the case of a write operation.

Abstract: In response to a tamper-attempt indication, a memory device selectively disables one or more memory operations. Disabling can be accomplished by different techniques, including altering bias voltages associated with performing the memory operation, gating off a current needed for performing the memory operation, and limiting the needed current to a magnitude below the threshold magnitude required for the operation. After disabling the memory operation, a mock current can be generated. The mock current is intended to mimic the current normally expended during the memory operation when not disabled, thereby leading a user to believe that the device is continuing to operate normally even though the memory operation that is being attempted is not actually being performed.

Abstract: A boosted supply voltage generator is selectively activated and deactivated to allow operations that are sensitive to variations on the boosted voltage to be performed with a stable boosted voltage. Techniques for deactivating and reactivating the voltage generator are also disclosed that enable more rapid recovery from deactivation such that subsequent operations can be commenced sooner. Such techniques include storing state information corresponding to the voltage generator when deactivated, where the stored state information is used when reactivating the voltage generator. Stored state information can include a state of a clock signal provided to the voltage generator.

Abstract: In some examples, a memory device may be configured to read or write multiple bit cells as part of the same operation. In some cases, the tunnel junctions forming the bit cells may be arranged to utilize shared read/write circuitry. For instance, the tunnel junctions may be arranged such that both tunnel junctions may be written using the same write voltages. In some cases, the bit cells may be configured such that each bit cell is driven to the same state, while in other cases, select bit cells may be driven high, while others are driven low.

Abstract: A memory system and memory controller for interleaving volatile and non-volatile memory accesses are described. In the memory system, the memory controller is coupled to the volatile and non-volatile memories using a shared address bus. Activate latencies for the volatile and non-volatile memories are different, and registers are included on the memory controller for storing latency values. Additional registers on the memory controller store precharge latencies for the memories as well as page size for the non-volatile memory. A memory access sequencer on the memory controller asserts appropriate chip select signals to the memories to initiate operations therein.

Abstract: Circuitry and a method provide a plurality of timed control and bias voltages to sense amplifiers and write drivers of a spin-torque magnetoresistive random access memory array for improved power supply noise rejection, increased sensing speed with immunity for bank-to-bank noise coupling, and reduced leakage from off word line select devices in an active column.

Abstract: A method of applying a write current to a magnetic tunnel junction device minimizes sub-threshold leakage. NMOS- and PMOS-follower circuits are used in applying the write current, and bias signals for the follower circuits are isolated from global bias signals before the write current is applied.

Abstract: A spin-torque magnetoresistive memory includes array read circuits and array write circuits coupled to an array of magnetic bits. The array read circuits sample magnetic bits in the array, apply a write current pulse to the magnetic bits to set them to a first logic state, resample the magnetic bits, and comparing the results of sampling and resampling to determine the bit state for each magnetic bit. For each of the magnetic bits in the page having the second logic state, the array write circuits initiate a write-back, wherein the write-back includes applying a second write current pulse having opposite polarity in comparison with the first write current pulse to set the magnetic bit to the second state. A read or write operation may be received after initiation of the write-back where the write-back can be aborted for a portion of the bits in the case of a write operation.

Abstract: In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to conserve power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving the word line to a first word line voltage. After such driving, the word line isolated. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell. Additional embodiments include the use of a supplemental voltage provider that is able to further boost or hold the isolated word line at the needed voltage level.

Abstract: A boosted supply voltage generator is selectively activated and deactivated to allow operations that are sensitive to variations on the boosted voltage to be performed with a stable boosted voltage. Techniques for deactivating and reactivating the voltage generator are also disclosed that enable more rapid recovery from deactivation such that subsequent operations can be commenced sooner. Such techniques include storing state information corresponding to the voltage generator when deactivated, where the stored state information is used when reactivating the voltage generator. Stored state information can include a state of a clock signal provided to the voltage generator.

Abstract: Circuitry and a method for regulating voltages applied to magnetoresistive bit cells of a spin-torque magnetoresistive random access memory (ST-MRAM) reduces time-dependent dielectric breakdown stress of the word line transistors. During a read or write operation, only the ends of the selected bit cells are pulled down to a low voltage and/or pulled up to a high voltage depending on the operation (write 0, write 1, and read) being performed. The ends of the unselected bit cells are held at a precharge voltage while separately timed signals pull up or pull down the ends of the selected bit cells during read and write operations.

Abstract: A boosted supply voltage generator is selectively activated and deactivated to allow operations that are sensitive to variations on the boosted voltage to be performed with a stable boosted voltage. Techniques for deactivating and reactivating the voltage generator are also disclosed that enable more rapid recovery from deactivation such that subsequent operations can be commenced sooner. Such techniques include storing state information corresponding to the voltage generator when deactivated, where the stored state information is used when reactivating the voltage generator. Stored state information can include a state of a clock signal provided to the voltage generator.

Abstract: In some examples, a memory device may be configured to read or write multiple bit cells as part of the same operation. In some cases, the tunnel junctions forming the bit cells may be arranged to utilize shared read/write circuitry. For instance, the tunnel junctions may be arranged such that both tunnel junctions may be written using the same write voltages. In some cases, the bit cells may be configured such that each bit cell is driven to the same state, while in other cases, select bit cells may be driven high, while others are driven low.

Abstract: In some examples, a memory device may be configured to utilize differential bit cells formed from two or more tunnel junctions. In some cases, the tunnel junctions forming the differential bit cell may be arranged to utilize shared read circuitry to reduce device mismatch. For instance, the read operations associated with both tunnel junction may be time multiplexed such that the same preamplifier circuitry may sense voltages representative of the tunnel junctions.

Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.