Abstract: A method of forming a shallow trench isolation structure comprising the following steps. A substrate having an upper surface is provided. A pad oxide layer is formed upon the substrate. A nitride layer is formed over the pad oxide layer. The nitride layer having an upper surface. A trench is formed by etching the nitride layer, pad oxide layer and a portion of the substrate. The trench having a bottom and side walls. An oxide film is deposited upon the etched nitride layer surface, and the bottom and side walls of trench. The oxide film is removed from over the etched nitride layer surface, and the bottom of the trench to expose a portion of substrate within the trench. The removal of oxide film leaving oxide spacers over the trench side walls. Epitaxial silicon is selectively deposited over the exposed portion of substrate, filling the trench. A thermal oxide layer is formed over the epitaxial silicon, annealing the interface between the epitaxial silicon and the oxide spacers.

Abstract: A method and means for detection of oxidizing contamination in acid etching baths employed to etch silicon oxide layers from silicon substrates employed in silicon integrated circuit microelectronics fabrications. There is provided a silicon substrate having within a doped region formed employing ion implantation. The silicon substrate is immersed within a buffered oxide etch (BOE) acid bath, wherein the presence of an oxidizing contaminant correlates with an increase in the resistance of the doped region upon the removal of any silicon oxide layer on the silicon surface.

Abstract: A method for forming a microelectronic layer. There is first provided a substrate. There is then formed over the substrate the microelectronic layer while employing a plasma enhanced chemical vapor deposition (PECVD) method employing a source material gas and a carrier gas, wherein there is employed a sufficiently low plasma power, a sufficiently low source material gas:carrier gas flow rate ratio and a sufficiently high carrier gas atomic mass such that the microelectronic layer is formed with enhanced film thickness uniformity. The method may be employed for forming ion implant screen layers, such as silicon oxide ion implant screen layers, with enhanced film thickness uniformity.

Abstract: A method of forming an interconnect, comprising the following steps. A semiconductor structure is provided that has an exposed first metal contact and a dielectric layer formed thereover. An FSG layer having a predetermined thickness is then formed over the dielectric layer. A trench, having a predetermined width, is formed within the FSG layer and the dielectric layer exposing the first metal contact. A barrier layer, having a predetermined thickness, may be formed over the FSG layer and lining the trench side walls and bottom. A metal, preferably copper, is then deposited on the barrier layer to form a copper layer, having a predetermined thickness, over said barrier layer covered FSG layer, filling the lined trench and blanket filling the barrier layer covered FSG layer. The copper layer, and the barrier layer on said upper surface of said FSG layer, are planarized, exposing the upper surface of the FSG layer and forming a planarized copper filled trench.

Abstract: Measurement of contaminating nitrogen during silicon ion implantation has been achieved by including a silicon wafer as a monitor in the implantation chamber. After silicon ion implantation, the monitor is subjected to a rapid thermal oxidation (about 1,100.degree. C. for one minute) and the thickness of the resulting grown oxide layer is measured. The thinner the oxide layer (relative to an oxide layer grown on pure silicon) the greater the degree of nitrogen contamination. For example, a reduction in oxide thickness of about 30 Angstroms corresponds to a nitrogen dosage of about 10.sup.13 atoms/sq. cm. By measuring total ion dosage during implantation and then subtracting the measured nitrogen dosage, the corrected silicon dosage may also be computed.